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FDC37N972 advance information advanced notebook i/o controller with enhanced keyboard control and system management features !" 3.3v operation with 5v tolerant buffers !" acpi 1.0 and pc99 compliant !" three power planes !" acpi embedded controller interface !" low standby current in sleep mode !" configuration register set compatible with isa plug-and-play standard (version 1.0a) !" serial irq interface compatible with serialized irq support for pci systems !" floppy disk interface on parallel port !" 8051 controller uses parallel port to reprogram the flash rom !" advanced infrared communications controller (ircc 2.0) - irda v1.1 (4mbps), hpsir, askir, consumer ir support - two ir ports - relocatable base i/o address !" 512k byte flash rom interface - 8051/host cpu multiplexed interface - sixteen 32k pages - 8051 keyboard bios - eight 64k pages - host system bios - embedded controller uses parallel port to reprogram flash rom !" isa host interface with clock run support and acpi sci interface - 16 bit address qualification - 8 bit data bus - zero wait-state i/o register access - shadowed write only registers - iochrdy for ecp, ircc 2.0 and flash cycles - 15 direct irqs including nsmi - four 8 bit dma channels - xnor test chain !" high-performance embedded 8051 keyboard and system controller - provides system power management - system watch dog timer (wdt) - 8042 style host interface - asynchronous access to two data registers and one status register - supports interrupt and polling access - 2k internal rom, nea pin select - 32k bank switchable external flash rom interface - 256 bytes data ram - on-chip control registers available via movx external data access commands - access to rtc and cmos registers - up to 16x8 keyboard scan matrix - three 16 bit timer/counters - integrated tx/rx serial interface - eleven 8051 interrupt sources - thirty-two 8 bit, host/8051 mailbox registers - thirty maskable hardware wake-up events supported - fast gatea20 - fast cpu_reset - multiple clock sources and frequencies - idle and sleep modes - fail-safe ring oscillator !" real time clock - mc146818 and ds1287 compatible - 256 bytes of battery backed cmos in two 128-byte banks - 128 bytes of cmos ram lockable in 4x32 byte blocks - 12 and 24 hour time format - binary and bcd format
2 - <2 ! a standby current (typ) !" two 8584-style access.bus controllers !" four independent hardware driven ps/2 ports !" general purpose i/o - 22 i/o pins - 12 out pins - eight in pins !" two programmable pulse-width modulator outputs - independent clock rates - 6 bit duty cycle granularity - vcc1 and vcc2 operation mode !" intelligent auto power management !" 2.88mb super i/o floppy disk controller - relocatable to 480 different base i/o addresses - 15 irq options - four dma options - open-drain/push-pull configurable output drivers - licensed cmos 765b floppy disk controller - advanced digital data separator - software and register compatible with smsc's proprietary 82077aa compatible core - low power cmos design with sophisticated power control circuitry (pcc) including multiple powerdown modes for reduced power consumption - supports two floppy drives on the fdd interface and two floppy drives on the parallel port interface - 12 ma fdd interface cable drivers with schmitt trigger inputs !" licensed cmos 765b floppy disk controller core - supports vertical recording format - 16-byte data fifo - 100% ibm compatibility - detects all overrun and underrun conditions - 12 ma drivers and schmitt trigger inputs - dma enable logic - data rate and drive control registers !" enhanced digital data separator - low cost implementation - no filter components required - 2 mbps, 1 mbps, 500 kbps, 300 kbps, 250 kbps data rates - programmable precompensation modes !" multi-mode parallel port with chiprotect - standard mode ibm pc/xt, pc/at, and ps/2 compatible bi-directional parallel port - enhanced parallel port epp 1.7 and epp 1.9 compatible (ieee 1284 compliant) ieee 1284 compliant enhanced capabilities port (ecp) - chiprotect circuitry to prevent printer power-on damage - relocatable to 480 different base i/o addresses - 15 irq options - 4 dma options - microsoft and hp compatible high speed mode - 12 ma output drivers !" serial port - high-speed ns16550a-compatible uart with 16-byte send/receive fifos - programmable baud rate generator modem control circuitry including 230k and 460k baud - relocatable to 480 different base i/o addresses - 15 irq options !" 208 pin tqfp package options !" 208 pin fbga package options
3 general description the FDC37N972 is a 208-pin 3.3v isa host acpi 1.0 and pc98 (/pc99)-compliant ultra i/o controller with fast infrared for mobile applications. the FDC37N972 incorporates a high- performance 8051-based keyboard controller; a 512k byte flash rom interface; four ps/2 ports; a real-time clock; smsc's true cmos 765b floppy disk controller with advanced digital data separator and 16-byte data fifo; an ns16c550a-compatible uart, smsc?s advanced infrared communications controller (ircc 2.0) with a uart and a synchronous communications engine to provide irda v1.1 (fast ir) capabilities; one multi-mode parallel port with chiprotect circuitry plus epp and ecp support; two 8584-style access bus controllers; a serial irq peripheral agent interface; an acpi embedded controller interface; general purpose i/o pins; two independently programmable pulse width modulators; two- floppy direct drive support; and maskable hardware wake-up events. the true cmos 765b core provides 100% compatibility with ibm pc/xt and pc/at architectures in addition to providing data overflow and underflow protection. the smsc advanced digital data separator incorporates smsc's patented data separator technology, allowing for ease of testing and use. the parallel port is compatible with ibm pc/at architecture, as well as epp and ecp. the 8051 controller can also take control of the parallel port interface to provide remote diagnostics or ?flashing? of the flash memory. the FDC37N972 has three separate power planes to provide ?instant on? and system power management functions. additionally, the FDC37N972 incorporates sophisticated power control circuitry (pcc). the pcc supports multiple low power down modes. wake-up events and acpi-related functions are supported through the sci interface. the FDC37N972?s configuration register set is compatible with the isa plug-and-play standard (version 1.0a) and provides the functionality to support windows '95. through internal configuration registers, each of the FDC37N972's logical device's i/o address, dma channel and irq channel may be programmed. there are 480 i/o address location options, 15 irq options, and four dma channel options for each logical device. the FDC37N972 does not require any external filter components and is, therefore, easy to use and offers lower system cost and reduced board area. the FDC37N972 is software and register compatible with smsc's proprietary 82077aa core.
4 table of contents feature s ...................................................................................................................................... . 1 general descriptio n ............................................................................................................... . 3 pin configuratio n ..................................................................................................................... . 9 description of pin function s ............................................................................................. . 11 functional descriptio n ........................................................................................................ . 28 floppy disk controlle r ....................................................................................................... . 30 fdc internal register s ..................................................................................................... . 30 status register encodin g ............................................................................................... . 44 fdc rese t ................................................................................................................................ . 46 fdc modes of operatio n ................................................................................................... . 47 dma transfer s ...................................................................................................................... . 47 controller phase s ................................................................................................................ . 47 fdc instruction se t ............................................................................................................ . 5 3 fdc data transfer command s ......................................................................................... . 6 4 acpi embedded controlle r ................................................................................................. . 8 2 eci configuration registers ........................................................................................... . 8 3 serial port (uart) ................................................................................................................... . 8 6 fifo interrupt mode operatio n ...................................................................................... . 9 7 fifo polled mode operatio n ............................................................................................ . 9 7 infrared communications controller (ircc 2.0 ) ......................................................... 102 overvie w ................................................................................................................................ 103 irrx/irtx pin enabl e ............................................................................................................. 104 ir registers - logical device 5 ........................................................................................ 104 ir dma channel s ................................................................................................................... 105 ir irq s ....................................................................................................................................... 105 ir half duplex timeou t ....................................................................................................... 106 irtx output pins default ................................................................................................... 106 parallel por t ....................................................................................................................... 106 the parallel port physical interface (pppi ) .............................................................. 1 2 8 parallel port fdc interfac e ........................................................................................... 1 2 9 auto power managemen t ..................................................................................................... 131 system power managemen t ............................................................................................. 131 dsr from powerdow n ....................................................................................................... 132 wake up from auto powerdow n .................................................................................... 132 register behavio r ............................................................................................................... 132 pin behavior ........................................................................................................................... 132 system interface pin s ........................................................................................................ 133
5 fdd interface pins ................................ ................................ ................................ ............... 134 uart power management ................................ ................................ ................................ .. 135 parallel port power management ................................ ................................ ................ 135 8051 embedded controller ................................ ................................ ................................ . 136 8051 functional overview ................................ ................................ ................................ . 136 powering up or resetting the 8051 ................................ ................................ ............... 137 cpu reset sequence ................................ ................................ ................................ ........... 140 8051 clock controls ................................ ................................ ................................ .......... 142 8051 ring oscillator fail-safe controls ................................ ................................ .... 144 8051 memory map ................................ ................................ ................................ ................... 145 flash rom interface ................................ ................................ ................................ ........... 152 8051 control registers ................................ ................................ ................................ ..... 153 8051 configuration/control memory mapped registers ................................ ......... 162 8051 interrupts ................................ ................................ ................................ ..................... 165 watch dog timer ................................ ................................ ................................ ..................... 183 wdt operation ................................ ................................ ................................ ...................... 183 wdt action ................................ ................................ ................................ ............................. 183 wdt activation ................................ ................................ ................................ ..................... 183 wdt reset mechanism ................................ ................................ ................................ ......... 183 wdt memory mapped registers ................................ ................................ ...................... 184 shared flash interface ................................ ................................ ................................ ....... 185 flash interface diagram ................................ ................................ ................................ ... 185 system memory map ................................ ................................ ................................ ............ 186 keyboard bios (kmem) ................................ ................................ ................................ ......... 187 system bios (hmem) ................................ ................................ ................................ .............. 189 host flash access ................................ ................................ ................................ .............. 189 idle mode ................................ ................................ ................................ ................................ 195 sleep mode ................................ ................................ ................................ ............................. 197 wake-up events ................................ ................................ ................................ .................... 201 8042 style host interface ................................ ................................ ................................ . 204 keyboard data write ................................ ................................ ................................ .......... 204 8051- to- host keyboard communication ................................ ................................ ...... 205 host-to 8051 keyboard communication ................................ ................................ ........ 206 gatea20 hardware speed-up ................................ ................................ ............................ 208 smsc ps/2 logic overview ................................ ................................ ................................ . 217 smsc ps/2 memory mapped control registers ................................ .......................... 218 devil logic overview ................................ ................................ ................................ .......... 225 the devil ps/2 logic commands ................................ ................................ ........................ 225 devil ps/2 memory mapped control registers ................................ .......................... 227
6 access.bus ................................ ................................ ................................ ................................ 233 background ................................ ................................ ................................ .......................... 233 register description ................................ ................................ ................................ ......... 234 access.bus interface description ................................ ................................ ................ 238 memory mapped control registers ................................ ................................ .............. 239 second i 2 c bus interface ................................ ................................ ................................ ..... 241 memory mapped control registers ................................ ................................ .............. 241 i 2 c clock divider bit ................................ ................................ ................................ ............ 243 overview ................................ ................................ ................................ ................................ 244 mailbox registers interface base address ................................ ............................... 246 mailbox registers ................................ ................................ ................................ ............... 247 the system/8051 interface registers` ................................ ................................ .......... 247 led controls ................................ ................................ ................................ ........................ 249 pulse width modulators ................................ ................................ ................................ .. 250 operation registers ................................ ................................ ................................ .......... 257 general purpose i/o (gpio) ................................ ................................ ................................ .. 260 overview ................................ ................................ ................................ ................................ 266 multiplexing_1 register ................................ ................................ ................................ ... 266 multiplexing_2 register ................................ ................................ ................................ ... 270 multiplexing_3 register ................................ ................................ ................................ ... 272 acpi pm1 block ................................ ................................ ................................ ......................... 276 acpi pm1 block overview ................................ ................................ ................................ ... 276 acpi pm1 block sci event-generating functions ................................ ...................... 276 acpi pm1 block base address ................................ ................................ ........................... 277 acpi pm1 block ................................ ................................ ................................ ...................... 278 registers ................................ ................................ ................................ ............................... 278 real time clock ................................ ................................ ................................ ....................... 283 general description ................................ ................................ ................................ .......... 283 configuration registers ................................ ................................ ................................ . 283 isa host i/o interface ................................ ................................ ................................ ......... 284 internal registers ................................ ................................ ................................ ............. 285 time calendar and alarm ................................ ................................ ................................ .. 286 update cycle ................................ ................................ ................................ ......................... 287 control and status registers ................................ ................................ ....................... 288 interrupts ................................ ................................ ................................ ............................. 292 frequency divider ................................ ................................ ................................ ............... 292 32 k h z clock input ................................ ................................ ................................ ................. 295 power management ................................ ................................ ................................ ............ 295
7 pci clock run support ................................ ................................ ................................ .......... 295 overview ................................ ................................ ................................ ................................ 295 serial interrupts ................................ ................................ ................................ ................... 298 serirq mode bit function ................................ ................................ ................................ . 299 FDC37N972 configuration ................................ ................................ ................................ .... 303 overview ................................ ................................ ................................ ................................ 303 configuration register access ................................ ................................ ..................... 303 chip level (global) control/configuration registers [0x00-0x2f] ..................... 308 logical device configuration/control registers [0x30-0xff] ............................. 311 i/o base address configuration register description ................................ .......... 313 interrupt select configuration register description ................................ ........ 315 dma channel select configuration register description ................................ ... 316 irq and dma enable and disable ................................ ................................ ...................... 317 smsc defined logical device configuration registers ................................ ......... 318 electrical specifications ................................ ................................ ................................ ... 327 maximum guaranteed ratings* ................................ ................................ ........................ 327 dc specifications ................................ ................................ ................................ ................ 328 ac specifications ................................ ................................ ................................ ................. 332 timing diagrams ................................ ................................ ................................ ...................... 333 load capacitance ................................ ................................ ................................ ................ 333 fast gatea20 iow timing ................................ ................................ ................................ ..... 334 isa io write ................................ ................................ ................................ ............................ 335 isa io read cycle ................................ ................................ ................................ .................. 336 dma timing (burst transfer mode) ................................ ................................ ................. 340 floppy disk drive timing (at mode) ................................ ................................ ................. 341 serial port timing ................................ ................................ ................................ ............... 342 parallel port timing ................................ ................................ ................................ .......... 343 epp 1.9 data or address write cycle ................................ ................................ ............ 344 epp 1.9 data or address read cycle ................................ ................................ .............. 346 epp 1.7 data or address write cycle ................................ ................................ ............ 348 epp 1.7 data or address read cycle ................................ ................................ .............. 350 ecp parallel port timing ................................ ................................ ................................ .. 351 access.bus timing ................................ ................................ ................................ ................ 355 host flash read timing ................................ ................................ ................................ ...... 356 host flash read/write ................................ ................................ ................................ ....... 358 zero wait state (nows) timing ................................ ................................ ........................ 360 flash program fetch timing ................................ ................................ ............................ 361 8051 flash read timing ................................ ................................ ................................ ........ 362 8051 flash write timing ................................ ................................ ................................ ...... 363
8 epp 1.7 data or address read cycle.............................................................................353 ecp parallel port timing..................................................................................................354 access.bus timing.............................................................................................................. ....358 host flash read timing......................................................................................................359 host flash read/write .......................................................................................................361 zero wait state (nows) timing.......................................................................................363 flash program fetch timing...........................................................................................364 8051 flash read timing ........................................................................................................3 65 8051 flash write timing ......................................................................................................36 6 ps/2 channel receive timing diagram ........................................................................367 ps/2 channel transmit timing diagram.....................................................................369 ps/2 channel ?bit-bang? timing ......................................................................................371 in circuit test (ict) ................................................................................................................ 373 appendix a ............................................................................................................................... .... 377 high-performance 8051 cycle timing and instruction set.............................377 appendix b ............................................................................................................................... .... 382 high performance 8051 extended interrupt unit................................................382
9 pin configuration figure 1 - FDC37N972 pin configuration for fbga ball pad configuration refer to figure 81 on page 372. 158 160 xosel xtal1 xtal2 agnd fad0 fad1 fad2 fad3 fad4 fad5 vss fad6 fad7 fa8 fa9 fa10 fa11 fa12 fa13 vcc1 fa14 fa15 fa16 fa17 fale nfrd nfwr nfcs gpio1 gpio2 gpio3 gpio4 gpio5 gpio6 gpio7 vss nea mode ab1_data ab1_clk nbat_led nfdd_led out11 out10 out9 out8 out7 gpio16 vcc2 gpio17 gpio18 gpio19 159 169 157 161 162 163 164 165 166 167 168 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 24mhz_out nec_sci vss 32khz_out vcc1_pwrgd npwr_led pwrgd slct pe busy nack pd7 pd6 pd5 pd4 vcc2 pd3 pd2 pd1 pd0 nslctin ninit nerror nalf nstrobe rxd txd vss ndsr nrts ncts ndtr ndcd nri gpio15 gpio14 gpio8 gpio9 vcc1 fa18 gpio10 gpio11 gpio12 in0 in1 in2 in3 in4 in5 in6 in7 vcc0 155 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 156 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 vcc2 clocki nreset_out ser_irq nclkrun pci_clk nmemwr nmemrd nromcs iochrdy tc drq1 ndack1 drq0 ndack0 vss sd7 sd6 sd5 sd4 sd3 vcc2 sd2 sd1 sd0 aen niow nior nnows out4 out3 vss out2 nirq8 out0 sa15 sa14 sa13 sa12 sa11 sa10 sa9 sa8 sa7 sa6 sa5 sa4 sa3 sa2 sa1 sa0 emdat 5 vss out5 out6 drvden0 drvden1 nmtr0 vss nds0 ndir nstep nwdata nwgate nhdsel nindex ntrk0 nwrtprt nrdata ndskchg fpd irtx irrx kso13 kso12 kso11 kso10 kso9 kso8 kso7 vcc1 kso6 kso5 kso4 kso3 kso2 kso1 kso0 ksi7 ksi6 ksi5 ksi4 ksi3 ksi2 ksi1 ksi0 gpio20 gpio21 imclk imdat vss kclk kdat emclk 21 1 2 3 4 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 FDC37N972 208 pin tqfp
10 figure 2 - FDC37N972 block diagram fdc37n97x (tikki) vcc1(3) vcc2(4) vss(9) rtc 2 x 128 byte banks of cmos ram bank 1 system reset host cpu interface control inputs pll clock generator bank 2 wdt configuration registers power management 8051 ring oscillator w/ fail safe 256b direct ram mailbox registers 8051 sub-block external control registers 256b external 8051 ram led driver general purpose i/o interface out in i/o i/o 16 x 8 keyboard interface 16c550 compatible serial port 1 infrared multi-mode parallel port / fdc mux ps/2 ports access bus access bus2 pwm flash interface control, address, data * -- alternate funciton vcc2 powered vcc1 powered ab_data, ab_clk ab2_data *, ab2_clk * pwm0*, pwm1* fad[0:7] fa[8:18], nfrd, nfwr, fale kclk, emclk, imclk, ps2clk ksi[0:7] ks0[0:13], ks0[14:15]* nbat_led, npwr_led, nfdd_led in0-7 out0-11 gpio 16-21 gpio 0-15 nslctin, ninit, nalf, nstrobe busy, slct, pe, nerror, nack pd[0:7] irrx2 irtx* irrx* txd, nrts, ndtr rxd, ncts, ndsr, ndcd nri nreset_out nior niow nmemrd nmemwr nromcs aen sa[0:15] sd[0:7] drq[0:1] drq[2:3]* ndack[0:1] tc ndack[2:3]* nirq8* nnows iochrdy mode nea 24mhz_out pwrgd 32khz_out vcc1_pwrgd clocki (14.318 mhz) xosel xtal2 xtal1 vcc0 agnd ndskchg, nwrtprt, ntrk0, nindex, fpd, ntrk0 nwgate, nhdsel, ndir, nstep, nds0, nds1*, nmtr0, nmtr1*, drvden0, drvden1*, fpd digital data separator with write precompensation smsc proprietary 82077 compatible vertical floppy disk controller core mdata mclock rdata rclock nwdata nrdata acpi embedded controller interrupts ser_irq pci_clk nclkrun nec_sci irtx2 nsmi* nfcs irmode / irrx3a, irmode / irrx3b pm1 block kdat, emdat, imdat, ps2dat
11 description of pin functions table 1 - FDC37N972 pin configuration tqfp pin# fgba pin# name tqfp pin# fgba pin# name tqfp pin# fgba pin# name 1 a1 vss 39 m3 ksi5 77 u8 nior 2 c2 out5 40 n4 ksi4 78 t9 niow 3 d4 out6 41 m1 ksi3 79 r9 aen 4 b1 drvden0 42 n2 ksi2 80 p10 sd0 5 c1 drvden1 43 n3 ksi1 81 u9 sd1 6 d2 nmtr0 44 n1 ksi0 82 t10 sd2 7 d3 vss 45 p1 gpio20 83 r10 vcc2 8 e4 nds0 46 p2 gpio21 84 p11 sd3 9 d1 ndir 47 p3 imclk 85 u10 sd4 10 e2 nstep 48 r1 imdat 86 t11 sd5 11 e3 nwdata 49 t1 vss 87 r11 sd6 12 f4 nwgate 50 r2 kclk 88 p12 sd7 13 e1 nhdsel 51 r3 kdat 89 u11 vss 14 f2 nindex 52 t2 emclk 90 t12 ndack0 15 f3 ntrk0 53 u1 emdat 91 r12 drq0 16 g4 nwrtprt 54 t3 sa0 92 p13 ndack1 17 f1 nrdata 55 p4 sa1 93 u12 drq1 18 g2 ndskchg 56 u2 sa2 94 t13 tc 19 g3 fpd 57 u3 sa3 95 r13 iochrdy 20 h4 irtx 58 t4 sa4 96 u13 nromcs 21 g1 irrx 59 r4 sa5 97 u14 nmemrd 22 h2 kso13 60 p5 sa6 98 t14 nmemwr 23 h3 kso12 61 u4 sa7 99 r14 pci_clk 24 j4 kso11 62 t5 sa8 100 u15 nclkrun 25 h1 kso10 63 r5 sa9 101 u16 ser_irq 26 j2 kso9 64 p6 sa10 102 t15 nreset_out 27 j3 kso8 65 u5 sa11 103 r15 clocki 28 k4 kso7 66 t6 sa12 104 t16 vcc2 29 j1 vcc1 67 r6 sa13 105 u17 24mhz_out 30 k2 kso6 68 p7 sa14 106 r16 nec_sci 31 k3 kso5 69 u6 sa15 107 p14 vss 32 l4 kso4 70 t7 out0 108 t17 32khz_out 33 k1 kso3 71 r7 out1 109 r17 vcc1_ pwrgd 34 l2 kso2 72 p8 out2 110 p16 npwr_led 35 l3 kso1 73 u7 vss 111 p15 pwrgd 36 m4 kso0 74 t8 out3 112 n14 slct 37 l1 ksi7 75 r8 out4 113 p17 pe 38 m2 ksi6 76 p9 nnows 114 n16 busy
12 tqfp pin# fgba pin# name tqfp pin# fgba pin# name tqfp pin# fgba pin# name 115 n15 nack 147 e15 gpio12 179 c10 fa16 116 m14 pd7 148 e17 in0 180 d9 fa17 117 n17 pd6 149 d17 in1 181 a10 fale 118 m16 pd5 150 d16 in2 182 b9 nfrd 119 m15 pd4 151 d15 in3 183 c9 nfwr 120 l14 vcc2 152 c17 in4 184 d8 nfcs 121 m17 pd3 153 b17 in5 185 a9 gpio1 122 l16 pd2 154 c16 in6 186 b8 gpio2 123 l15 pd1 155 c15 in7 187 c8 gpio3 124 k14 pd0 156 b16 vcc0 188 d7 gpio4 125 l17 nslctin 157 a17 xosel 189 a8 gpio5 126 k16 ninit 158 b15 xtal1 190 b7 gpio6 127 k15 nerror 159 d14 xtal2 191 c7 gpio7 128 j14 nalf 160 a16 agnd 192 d6 vss 129 k17 nstrobe 161 a15 fad0 193 a7 nea 130 j16 rxd 162 b14 fad1 194 b6 mode 131 j15 txd 163 c14 fad2 195 c6 ab1_data 132 h14 vss 164 d13 fad3 196 d5 ab1_clk 133 j17 ndsr 165 a14 fad4 197 a6 nbat_led 134 h16 nrts 166 b13 fad5 198 b5 nfdd_led 135 h15 ncts 167 c13 vss 199 c5 out11 136 g14 ndtr 168 d12 fad6 200 a5 out10 137 h17 ndcd 169 a13 fad7 201 a4 out9 138 g16 nri 170 b12 fa8 202 b4 out8 139 g15 gpio15 171 c12 fa9 203 c4 out7 140 f14 gpio14 172 d11 fa10 204 a3 gpio16 141 g17 gpio8 173 a12 fa11 205 a2 vcc2 142 f16 gpio9 174 b11 fa12 206 b3 gpio17 143 f15 vcc1 175 c11 fa13 207 c3 gpio18 144 e14 fa18 176 d10 vcc1 208 b2 gpio19 145 f17 gpio10 177 a11 fa14 146 e16 gpio11 178 b10 fa15 vcc2 vcc1 vcc0
13 device functions per pin are shown in table 2 . buffer modes symbols in table 2 are described in table 3. multifunction pins are summarized in table 4, including a multiplex controls reference. the pins and descriptions in table 2 are organized by primary pin function. for example, the ps2 serial clock and ps2 serial data pins are technically part of the keyboard and mouse interface but are listed in the general purpose i/o interface because the gpio function of these pins is the default. table 2 - pin function description tqfp pin# notes name description power plane buffer modes 2 fdd interface (15) the following fdc output pins can be configured as either open drain outputs capable of sinking 12ma (od12) or as push-pull outputs capable of driving 6ma and sinking 12ma (o12). the fdc output pins must tristate when the fdc is in powerdown mode (the board designer must provide external pull-up resistors on these output pins). 4 drvden0 drive density select 0 vcc2 (o12/od12) 5 drvden1 drive density select 1 vcc2 (o12/od12) 6 nmtr0 motor on 0 vcc2 (o12/od12) 8 nds0 drive select 0 vcc2 (o12/od12) 9 ndir step direction vcc2 (o12/od12) 10 nstep step pulse vcc2 (o12/od12) 11 nwdata write disk data vcc2 (o12/od12) 12 nwgate write gate vcc2 (o12/od12) 13 nhdsel head select vcc2 (o12/od12) 14 nindex index pulse input vcc2 is 15 ntrk0 track 0 vcc2 is 16 nwrtprt write protected vcc2 is 17 nrdata read disk data vcc2 is 18 ndskchg disk change vcc2 is 19 fpd floppy power down output control vcc2 o8 pci power management and sirq interface (4) 106 7 n ec_sci power management event vcc1 pci_od 99 pci_clk pci clock vcc2 pci_iclk 101 ser_irq serial irq vcc2 pci_io 100 nclkrun pci clock control vcc2 pci_od isa host interface (37) 80: 82, 84: 88 sd[7:0] system data bus vcc2 io12 54: 69 sa[15:0] system address bus vcc2 i 96 nromcs rom chip select vcc2 i 79 aen address enable vcc2 i 95 iochrdy i/o channel ready vcc2 od12 91, 93 drq[1:0] dma requests vcc2 o12
14 tqfp pin# notes name description power plane buffer modes 2 90, 92 ndack[1:0] dma acknowledge vcc2 i 94 tc terminal count vcc2 i 77 nior i/o read vcc2 i 78 niow i/o write vcc2 i 97 nmemrd memory read vcc2 i 98 nmemwr memory write vcc2 i 76 nnows no wait state vcc2 od12 flash rom interface (23) 161: 166, 168, 169 fad[7:0] flash address/data[7:0] bus vcc1 io8 170: 175, 177: 180 fa[8:17] flash address[17:8] note : upper address bit fa18 is multiplexed on gpio13 vcc1 o8 144 5 fa18/ gpio13 (wk_se17) flash address 18 general purpose i/o vcc1 o8/io8 182 nfrd flash memory read vcc1 o8 183 nfwr flash memory write vcc1 o8 181 fale flash address latch enable vcc1 o8 184 5 nfcs/ gpio0 (wk_se02) flash rom chip select general purpose i/o vcc1 o8/io8 keyboard and mouse interface (29) 30: 36, 24: 28 kso[0:11] keyboard scan outputs (14 8). note: gpio4 and gpio5 can be configured as kso14 and kso15 (16 8). vcc1 od4 23 3 kso12/ out8/ kbrst keyboard scan output general purpose output cpu_reset vcc1 od4/od4/ od4 22 11 kso13/ gpio18 keyboard scan output general purpose i/o vcc1 od4/iod4 37:44 ksi[0:7] keyboard scan inputs vcc1 isp 193 nea external access for 2k rom vcc1 i 52 emclk em serial clock vcc2 iod16 53 emdat em serial data vcc2 iod16 47 imclk im serial clock vcc2 iod16 48 imdat im serial data vcc2 iod16 51 kdat keyboard data vcc2 iod16
15 tqfp pin# notes name description power plane buffer modes 2 50 kclk keyboard clock vcc2 iod16 general purpose i/o interface (40) 70 7,8 out0 (sci) general purpose output (sci) vcc1 (o12/od12) 71 3 out1/ nirq8 general purpose output/ active low rtc irq vcc1 o12/o12 72 out2 general purpose output vcc1 o12 74 out3/ frw general purpose output inverted flash rom memory write vcc1 o12/o12 75 out4 general purpose output vcc1 o12 2 3 out5/ nds1/ kbrst general purpose output fdd drive select 1 3 cpu_reset 3 vcc1 o12/(o12/ od12)/o12 3 3 out6/ nmtr1 general purpose output fdd motor on 1 vcc1 o12/(o12/ od12) 203 3 out7/ nsmi general purpose output smi output vcc1 o12/od12 202 3 out8/ drq2/ kbrst general purpose output dma request cpu_reset vcc1 o12/o12/ o12 201 3 out9/ drq3 general purpose output dma request vcc1 o12/o12 200 out10/ pwm0 general purpose output pulse width modulator output vcc1 o12/o12 199 out11/ pwm1 general purpose output pulse width modulator output vcc1 o12/o12 148 4 in0 (wk_ee4) general purpose input vcc1 i 149 4 in1 (wk_ee2) general purpose input vcc1 i 150 4 in2 (wk_ee3) general purpose input vcc1 i 151 in3 (ngpwkup) general purpose input (general purpose wake up) vcc1 i 152 5 in4 (wk_se00) general purpose input vcc1 i 153 5 in5 (wk_se01) general purpose input vcc1 i 154 5 in6 (wk_se05) general purpose input vcc1 i 155 4 in7 (wk_ee1) general purpose input vcc1 i 185 5 gpio1 (wk_se03) general purpose i/o vcc1 io8
16 tqfp pin# notes name description power plane buffer modes 2 186 5 gpio2 (wk_se04) general purpose i/o vcc1 io8 187 6 gpio3 (trigger) general purpose i/o (interrupt 1 event) vcc1 io8 188 5 gpio4 (wk_se07)/ kso14 general purpose i/o keyboard scan output vcc1 io8/od8 189 5 gpio5 (wk_se10)/ kso15 general purpose i/o keyboard scan output vcc1 io8/od8 190 5 gpio6 (wk_se11)/ irmode/irr x3a general purpose i/o fir mode output or 2 nd receive input vcc1 io8/(o8/i) 191 5, 8 gpio7 (wk_se06) 5 general purpose i/o vcc1 (io8/iod8) 8 141 5 gpio8 (wk_se12)/ irrx2 general purpose i/o ir receive input vcc1 io8/i 142 1, 5 gpio9 (wk_se13)/ irtx2 general purpose i/o ir transmit output vcc1 io12/o12 145 5 gpio10 (wk_se14)/ irmode/irr x3b general purpose i/o fir mode output or 2 nd receive input vcc1 io8/o8/ (o8/i) 146 5 gpio11 (wk_se15)/ ab2_data general purpose i/o access.bus 2 serial data vcc1 io12/iod12 147 5 gpio12 (wk_se16)/ ab2_clk general purpose i/o access.bus 2 clock vcc1 io12/iod12 140 5 gpio14 (wk_se20) general purpose i/o vcc1 io8 139 5 gpio15 (wk_se21) general purpose i/o vcc1 io8 204 5 gpio16 (wk_se22) 5 general purpose i/o vcc1 io8 206 3, 5 gpio17 (wk_se23)/ gatea20 general purpose i/o kbd gatea20 output vcc1 io8/o8
17 tqfp pin# notes name description power plane buffer modes 2 207 5 gpio18 (wk_se27)/ ndack2 general purpose i/o/ dma acknowledge vcc1 io8/i 208 5 gpio19 (wk_se24)/ ndack3 general purpose i/o/ dma acknowledge vcc1 io8/i 45 3, 5 gpio20 (wk_se25)/ ps2clk/ 8051rx/ general purpose i/o ps2 serial clock 8051 rx input vcc1 iod16/ iod16/i 46 3,5 gpio21 (wk_se26)/ ps2dat/ 8051tx general purpose i/o ps2 serial data 8051 tx input vcc1 iod16/ iod16/ od16 infrared interface (2) 21 irrx ir receive input vcc1 i 20 1 irtx ir transmit output vcc2 o12 parallel port interface (17) 126 ninit/ ndir initiate output fdc direction control vcc2 (od14/ op14)/od14 125 nslctin/ nstep printer select input fdc step pulse vcc2 (od14/ op14)/od14 124 pd0/ nindex port data 0 fdc index vcc2 iop14/i 123 pd1/ ntrk0 port data 1 fdc track 0 vcc2 iop14/i 122 pd2/ nwrtprt port data 2 fdc write protected vcc2 iop14/i 121 pd3/ nrdata port data 3 fdc read disk data vcc2 iop14/i 119 pd4/ ndskchg port data 4 fdc disk change vcc2 iop14/i 118 pd5 port data 5 vcc2 iop14 117 pd6/ nmtr0 port data 6 fdc motor on 0 vcc2 iop14/od14 116 pd7 port data 7 vcc2 iop14 112 slct/ nwgate printer selected status fdc write gate vcc2 i/od12 113 pe/ nwdata paper end fdc write data vcc2 i/od12 114 busy/ nmtr1 busy fdc motor on 1 vcc2 i/od12
18 tqfp pin# notes name description power plane buffer modes 2 115 nack/ nds1 acknowledge fdc drive select 1 vcc2 i/od12 127 nerror/ nhdsel error fdc head select vcc2 i/od12 128 nalf/ drvden0 autofeed output fdc density select 0 vcc2 (od14/op14)/ od14 129 nstrobe/ nds0 strobe output fdc drive select 0 vcc2 (od14/op14)/ od14 serial port interface (8) 130 rxd receive data vcc2 i 131 txd transmit data vcc2 o12 133 ndsr data set ready vcc2 i 134 nrts request to send vcc2 o8 135 ncts clear to send vcc2 i 136 ndtr data terminal ready vcc2 o8 138 nri ring indicator vcc1 i 137 ndcd data carrier detect vcc2 i miscellaneous (11) 108 32khz_out 32.768khz output clock --the 32 khz output is enabled / disabled by setting / clearing bit-0 of the output enable 8051 memory mapped register. when disabled the 32 khz_out pin is driven low. the 32 khz_out pin defaults to the disabled state on vcc1 por. vcc1 o8 105 24mhz_out 24mhz clock output programmable clock output. 1.8432 mhz (default = 24 mhz/13) 14.318 mhz 16 mhz 24 mhz 48 mhz vcc2 o24 103 clocki 14.318mhz clock input vcc2 iclk 194 mode configuration ports base address select vcc1 i 157 10 xosel external 32khz clock enable input vcc0 i
19 tqfp pin# notes name description power plane buffer modes 2 109 9 vcc1_pwr gd vcc1 power good input. the trailing edge of vcc1 por is released 20ms from the assertion of this pin. if this pin is pulled low while vcc1 is valid, then vcc1 por will be asserted and held until 20ms from re-assertion of this pin. this pin has an internal weak (90 m a) pull-up to vcc1. vcc1 ip 102 nreset_out system reset vcc2 o8 197 nbat_led battery led (0 = on) vcc1 od12 110 npwr_led power led (0 = on) vcc1 od12 198 nfdd_led floppy led (0 = on). this pin is asserted whenever either drvsel1 or drvsel0 is asserted or controlled by the 8051. vcc1 od12 111 9 pwrgd vcc2 power good input vcc1 i access bus interface (2) 195 ab1_data access.bus 1 serial data vcc1 iod12 196 ab1_clk access.bus 1 clock vcc1 iod12 real time clock interface (2) 158 xtal1 32.768khz crystal input vcc0 iclk2 159 10 xtal2 32.768khz crystal output vcc0 (oclk2/i) power planes 156 vcc0 rtc (v bat ) supply voltage 29, 143, 176, vcc1 +3.3v 5% main battery supply 83, 104, 120, 205 vcc2 +3.3v 5% switched ac/main battery supply 160 agnd analog ground 1,7,49, 73, 89, 107, 132, 167, 192 vss digital ground
20 note 1: these pins default to ?output?, ?low? to prevent infrared transceiver damage (see section irtx output pins default ). note 2: buffer modes per function on multiplexed pins are separated by a slash ?/?; e.g., a pin with two multiplexed functions where the primary function is an input and the secondary function is an 8ma bidirectional driver is represented as ?i/io8?. buffer modes in parenthesis represent multiple buffer modes for a single pin function. note 3: this pin is tristated w hen pwrgd is inactive and the pin is configured as a vcc2- powered alternate function. note 4: these devices can generate wake-up events on either edge of the signal that is applied when the pin is configured as an input. the interrupts are masked by the wake-up mask register bits. note 5: these devices can generate wake-up events on selectable edges of the signal that is applied when the pin is configured as an input. the interrupts are masked by the wake-up mask registers and selected edges are programmed via the edge select registers (see section 8051 internal parallel on page 170). note 6: this interrupt is masked by int1 mask register bit 3. gpio3 is the only gpio pin which does not generate a wakeup event. note 7: the nec_sci pin can be controlled by hardware and 8051 software. the nec_sci pin can drive either the acpi run-time gpe chipset input or the wake gpe chipset input ( figure 7 ). depending how the nec_sci pin is used, other acpi-related sci functions may be best supplied by FDC37N972 general purpose output out0. note 8: out0 and gpio7 are suitable as an sci output pin because the buffer type can be configured as a push-pull or open-drain output (see a description of the misc21 and misc23 bits in multiplexing_3 register on page 278). note 9: i nput levels for the pwrgd and vcc1_pwrgd pins are rail-to-rail 400mv; e.g., pwrgd v il = .4v max, pwrgd v ih = 2.7v min. @ vcc1 min. note 10: the function of these pins are described in section 32khz clock input the FDC37N972 uses the xosel pin to select either a 32.768khz input clock or a 32.768khz crystal to drive the real time clock interface (table 2 - pin function description). when xosel = ?0?, the rtc uses a 32.768khz crystal connected between the xtal1 and xtal2 pins. when xosel = ?1?, the rtc is driven by a 32.768khz single-ended clock source connected to the xtal2 pin. note: icc0 3 3 10 m a for time-keeping operations under vcc0 using a single-ended clock source. icc1 = 30 m a under vcc1 using a single-ended clock source. note 11: the gpio18 altern ate function of the ks013 pin has no wake-up capability (see note following).
21 table 3 - buffer mode legend buffer symbol description i input io12 bidirectional ? 12ma sink, 6ma source io8 bidirectional ? 8ma, 4ma source iod16 input, open drain output ? 16ma sink iod8 input, open drain output ? 8ma sink iop14 bidirectional ? 14ma sink, 14ma source, backdrive protected ip input with pullup is schmitt trigger input isp schmitt trigger input with pullup o12 output ? 12ma, 6ma source o8 output ? 8ma, 4ma source od12 open drain ? 12ma sink od14 open drain ? 14ma sink od16 open drain ? 16ma sink od4 open drain ? 4ma sink od8 open drain ? 8ma sink op14 output ? 14ma sink, 14ma source, backdrive protected pci_iclk pci clock input pci_io pci bidirectional pci_od pci open drain iclk clock input iclk2 clock input 2 oclk2 clock output 2 o24 output ? 12ma, 6ma source
22 table 4 - alternate function pins default function 2 alternate function #1 alternate function #2 multiplex controls out1 vcc1 nirq8 3 vcc2 - misc0 out3 vcc1 fwr vcc1 - - alt write select 6 out5 vcc1 nds1 3 vcc2 kbrst 3 vcc2 misc[5, 22] 5 out6 vcc1 nmtr1 3 vcc2 - - misc5 out7 vcc1 nsmi 3 vcc2 - misc18 1 out8 vcc1 drq2 3 vcc2 kbrst 3 vcc2 misc[17,10, 6] out9 vcc1 drq3 3 vcc2 - misc11 out10 vcc1 pwm0 vcc1 - misc4 out11 vcc1 pwm1 vcc1 - misc12 1 nfcs vcc1 gpio0 vcc1 - misc19 1 gpio4 vcc1 kso14 vcc1 - gpio5 vcc1 kso15 vcc1 - misc9 gpio6 vcc1 irmode/ir rx3a 3 vcc2 - misc[14:13] gpio8 vcc1 irrx vcc1 - gpio9 vcc1 irtx 4 vcc2 - misc[2,7] gpio10 vcc1 irmode/ir rx3b 3 vcc2 - misc[16:15] gpio11 vcc1 ab2_data vcc1 gpio12 vcc1 ab2_clk vcc1 misc20 fa18 vcc1 gpio13 vcc1 - misc8 1 gpio17 vcc1 gatea20 3 vcc1 - misc6 gpio18 vcc1 ndack2 vcc1 - misc17 gpio19 vcc1 ndack3 vcc1 - misc11 gpio20 vcc1 ps2clk 3 vcc2 8051rx vcc1 gpio21 vcc1 ps2dat 3 vcc2 8051tx vcc1 misc[3, 1] kso12 vcc1 out8 vcc1 kbrst 3 vcc2 misc[17, 10, 6] kso13 vcc1 gpio18 vcc1 - misc17
23 default function 2 alternate function #1 alternate function #2 multiplex controls ninit vcc2 ndir vcc2 - nslctin vcc2 nstep vcc2 - pd0 vcc2 nindex vcc2 - pd1 vcc2 ntrk0 vcc2 - pd2 vcc2 nwrtprt vcc2 - pd3 vcc2 nrdata vcc2 - pd4 vcc2 ndskchg vcc2 - pd6 vcc2 nmtr0 vcc2 - slct vcc2 nwgate vcc2 - pe vcc2 nwdata vcc2 - busy vcc2 nmtr1 vcc2 - nack vcc2 nds1 vcc2 - nerror vcc2 nhdsel vcc2 - nalf vcc2 drvden0 vcc2 - nstrobe vcc2 nds0 vcc2 - cr25[4:3] note 1: see a description in section multifunction pin on page 271. note 2: the fdc37n9 72 pins are identified by primary pin function (see description of pin functions on page 11 ). note that some functions are available on more than one pin; e.g., out8, gpio18 and kbrst. note 3: when this pin is configured as an alternate function output and pwrgd is inactive, i.e. vcc2 is 0v, the pin will tri-state to prevent back-biasing of external circuitry (see section general purpose i/o (gpio) on page 265). note 4: this pin defaults to ?output?, ?low? for both the defaul t (gpio) function and the alternate (irtx) function, regardless of the state of pwrgd (see section general purpose i/o (gpio) on page 265). note 5: misc5 must be inactive for misc22 to enable kbrst. note 6: the alt write select bit is in the flash configu ration register (see section alt write select bit, d3 on page 197).
24 there are three power planes in the FDC37N972 v cc0, v cc1, and v cc2 with the following power sequencing requirement: 1. v cc2 shall have power applied simultaneously with or after v cc1 . 2. v cc 1 shall have power applied simultaneously with or after v cc0 . all internal components which utilize v cc0 power plane are switched internally between the vcc1 and vcc0 pins according to vcc1_pwrgd see table 5 for power consumption in various states. two FDC37N972 power supply configurations can be utilized. these power supply configuration types fundamentally differ upon the need for a backup battery (v bat ) connection to v cc0 . type 1 devices do not require a v cc0 battery connection. power supply requirements for type 1 devices are as follows: v cc0 is tied to v ss , v cc1 is connected to the main battery supply, and v cc2 is switched from either the main battery or ac power if available. in this configuration all internal components which utilize v cc0 power plane are switched internally to the vcc1 upon por according to vcc1_pwrgd. type 2 devices require a v cc0 battery connection. power supply requirements for type 2 devices are as follows: v cc0 is connected to a backup battery (v bat ), v cc1 is connected to the main battery supply, and v cc2 is switched from either the main battery or ac power if available. in this configuration all internal components which utilize v cc0 power plane only when v cc1 is absent. normally (when vcc1_pwrgd is asserted) they are switched internally to the vcc1 power plane.
25 table 5 - power comsumption in various states v cc2 (vdc) v cc1 (vdc) 8051 state clock state sym typ max comments 3.3 3.3 run 24 mhz i cc2 i cc1 15 ma 24 ma 20 ma 30 ma floppy @ 1 meg data rate i2c @ 24 mhz 3.3 3.3 run 12 mhz i cc2 i cc1 13 ma 12 ma 15 ma 18 ma floppy @ 500k data rate i2c @ 12 mhz 3.3 3.3 run ring osc i cc2 i cc1 >1ma 8 ma 2 ma 10 ma pll on i2c off 3.3 3.3 idle ring osc i cc2 i cc1 >1ma 5 ma 2 ma 7 ma pll off 0 3.3 run ring osc i cc2 i cc1 8 ma 10 ma pll off i2c off 0 3.3 idle ring osc i cc2 i cc1 6 ma 8 ma pll off i2c off 0 3.3 sleep stop i cc1 160 a xosel=1 0 3.3 sleep stop i c c1 5 a 10 a xosel=0 0 0 i cc0 40 a 60 a 2.4 < v cc0 < 4 vdc, xosel=1, 0 0 i cc0 0.4 a 1.5 a 2.4 < v cc0 < 4 vdc, xosel = 0 note: when a single-ended 32.768khz clock source is selected (see section 32khz clock input). the FDC37N972 uses the xosel pin to select either a 32.768khz input clock or a 32.768khz crystal to drive the real time clock interface (table 2 - pin function description). when xosel = ?0?, the rtc uses a 32.768khz crystal connected between the xtal1 and xtal2 pins. when xosel = ?1?, the rtc is driven by a 32.768khz single- ended clock source connected to the xtal2 pin.
26 table 7 - power pin list bias pins 156 vcc0 rtc (v bat )supply voltage 2.7-3.3v ibat<2ma 29, 143, 176 vcc1 8051 + ab + ci + rtc+ acpi + pm1 + wdt + mr + cr + pm + ab2 + fi + pwm + ki + gpio + led + ir + 3.3v +/-5% supply voltage (note) 83, 104, 120, 205 vcc2 sr + pcg + fdc + dds + uart + pp + ps/2 + core +3.3v +/-5%supply voltage 160 agnd analog ground for vcc0. 1, 7, 49, 73, 89, 107, 132, 167, 192 vss digital ground note: ab = access.bus ci = control inputs wdt = watch dog timer mr = mailbox registers cr = control registers pm = power management ab2 = access. bus 2 fi = f lash interface ki = keyboard interface gpio = general purpose i/o interface ir = infrared sr = system reset pcg = pll clock generator fdc = floppy disk controller dds = digital data seperator pp = multi-mode parallel port pwrgd and vcc1_pwrgd timing is illustrated in figure 3 through figure 5 .
27 pwrgd vcc2 clocki 10 m s 3v min. figure 3 ? power-fail event pwrgd vcc2 3v clocki 10 m s min. figure 4 - vcc2 power-up timing vcc1_pwrgd vcc1 3v 3v 1 m s min. 1 m s min. figure 5 - vcc1_pwrgd timing these figures also appear in the ?timing diagrams? section of this spec.
28 functional description FDC37N972 operating registers the address map, shown below in table 8 , shows the set of operating registers and addresses for each of the logical blocks of the FDC37N972 ultra i/o controller. the base addresses of the fdc, parallel, serial 1 and infrared ports can be moved via the configuration registers. host processor interface the host processor communicates with the FDC37N972 through a series of read/write registers. the range of base i/o port addresses for these registers is shown in table 8 . register access is accomplished through programmed i/o or dma transfers. all registers are 8 bits. most of the registers support zero wait-state access (nows). all host interface output buffers are capable of sinking a minimum of 6 ma. table 8 - FDC37N972 operating register addresses logical device number logical device base i/o range (note3) fixed base offsets isa cycle type 0x00 fdc [0x100:0x0ff8] on 8 byte boundaries +0 : sra +1 : srb +2 : dor +3 : tsr +4 : msr/dsr +5 : fifo +7 : dir/ccr nows 0x03 parallel port [0x100:0x0ffc] on 4 byte boundaries (epp not supported) or [0x100:0x0ff8] on 8 byte boundaries (all modes supported, epp is only available when the base address is on an 8- byte boundary) +0 : data / ecpafifo +1 : status +2 : control +400h : cfifo / ecpdfifo tfifo / cnfga +401h : cnfgb +402h : ecr std. isa i/o
29 logical device number logical device base i/o range (note3) fixed base offsets isa cycle type 0x04 serial port 1 [0x100:0x0ff8] on 8 byte boundaries +0 : rb/tb ? lsb div +1 : ier ? msb div +2 : iir/fcr +3 : lcr +4 : mcr +5 : lsr +6 : msr +7 : scr nows 0x05 infrared port [0x100:0x0ff8] on 8 byte boundaries +0 : rb/tb ? lsb div +1 : ier ? msb div +2 : iir/fcr +3 : lcr +4 : mcr +5 : lsr +6 : msr +7 : scr nows 0x62, 0x63 [0x100:0x0ff8] on 8 byte boundaries +0 : register block n, address 0 +1 : register block n, address 1 +2 : register block n, address 2 +3 : register block n, address 3 +4 : register block n, address 4 +5 : register block n, address 5 +6 : register block n, address 6 +7 : sce master control reg. 0x06 rtc not relocatable fixed base address 0x70, 0x74 : address register 0x71, 0x76 : data register nows std. isa i/o 0x07 kybd not relocatable fixed base address 0x60 : data register 0x64 : command/status reg. nows note 1: refer to the configuration register descriptions for setting the base address note 2: this chip uses all isa address bits to decode the base address of each of its logical devices.
30 floppy disk controller the floppy disk controller (fdc) provides the interface between a host microprocessor and the floppy disk drives (fdd). the fdc integrates the functions of the formatter/controller, digital data separator, write precompensation and data rate selection logic for an ibm xt/at compatible fdc. the true cmos 765b core guarantees 100% ibm pc xt/at compatibility in addition to providing data overflow and underflow protection. the fdc is compatible to the 82077aa using smsc's proprietary fdc core. fdc internal registers the fdc contains eight internal registers, which facilitate the interfacing between the host microprocessor and the disk drive table 9 shows the addresses required toaccess these registers. registers other than the ones shown are not supported. table 9 - status, data and control registers fdc primary base i/o address offset r/w register 0 r status register a (sra) 1 r status register b (srb) 2 r/w digital output register (dor) 3 r/w tape drive register (tdr) 4 r main status register (msr) 4 w data rate select register (dsr) 5 r/w data (fifo) 6 reserved 7 r digital input register (dir) 7 w configuration control register (ccr) status register a (sra) fdc i/o base address + 0x00 (read only) this register is read-only and monitors the state of the fdc interrupt pin and several disk interface pins in ps/2 and model 30 modes. the sra can be accessed at any time when in ps/2 mode. in the pc/at mode the data bus pins d0 - d7 are held in a high impedance state for a read of sra.
31 table 10 - srb - ps/2 model 30 mode 7 6 5 4 3 2 1 0 int pending ndrv2 step ntrk0 hdsel nindx nwp dir reset cond. 0 n/a 0 n/a 0 n/a n/a 0 bit 0 direction active high status indicating the direction of head movement. a logic "1" indicates inward direction; a logic "0" indicates outward direction. bit 1 nwrite protect active low status of the write protect disk interface input. a logic "0" indicates that the disk is write protected. bit 2 nindex active low status of the index disk interface input. bit 3 head select active high status of the hdsel disk interface input. a logic "1" selects side 1 and a logic "0" selects side 0. bit 4 ntrack 0 active low status of the trk0 disk interface input. bit 5 step active high status of the step output disk interface output pin. bit 6 ndrv2 active low status of the drv2 disk interface input pin, indicating that a second drive has been installed. bit 7 interrupt pending active high bit indicating the state of the floppy disk interrupt output.
32 table 11 - sra - ps/2 model 30 mode 7 6 5 4 3 2 1 0 int pending drq step f/f trk0 nhdse l indx wp ndir reset cond. 0 0 0 n/a 1 n/a n/a 1 bit 0 ndirection active low status indicating the direction of head movement. a logic "0" indicates inward direction; a logic "1" indicates outward direction. bit 1 write protect active high status of the write protect disk interface input. a logic "1" indicates that the disk is write protected. bit 2 index active high status of the index disk interface input. bit 3 nhead select active low status of the hdsel disk interface input. a logic "0" selects side 1 and a logic "1" selects side 0. bit 4 track 0 active high status of the trk0 disk interface input. bit 5 step active high status of the latched step disk interface output pin. this bit is latched with the step output going active, and is cleared with a read from the dir register, or with a hardware or software reset. bit 6 dma request active high status of the fdc?s drq output pin. bit 7 interrupt pending active high bit indicating the state of the floppy disk interrupt output.
33 digital output register (dor) fdc i/o base address + 0x02 (read/write) the dor controls the drive select and motor enables of the disk interface outputs. it also contains the enable for the dma logic and a software reset bit. the contents of the dor are unaffected by a software reset. the dor can be written to at any time. t able 12 - fdc dor 7 6 5 4 3 2 1 0 mot en3 mot en2 mot en1 mot en0 dmaen nrese t drive sel1 drive sel0 reset cond. 0 0 0 0 0 0 0 0 bit 0 and 1 drive select these two bits are binary encoded for the two drive selects output pins nds0 and nds1, thereby allowing only one drive to be selected at one time. bit 2 nreset a logic ?0? written to this bit resets the fdc. this reset will remain active until a logic ?1? is written to this bit. this software reset does not affect the dsr and ccr registers, nor does it affect the other bits of the dor register. the minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset. bit 3 dmaen pc/at and model 30 mode: writing this bit to logic ?1? will enable the fdc?s ndack and tc inputs and enable the fdc?s drq and interrupt outputs. this bit being a logic ?0? will disable the fdc?s ndack and tc inputs, and hold the fdc?s drq and interrupt outputs in a high impedance state. this bit is a logic ?0? after a reset. ps/2 mode: in this mode the tc and the fdc?s drq, ndack, and interrupt pins are always enabled. during a reset, the drq, ndack, tc, and interrupt pins will remain enabled, but this bit will be cleared to a logic ?0?. bit 4 motor enable 0 this bit controls the nmtr0 disk interface output. a logic ?1? in this bit will cause the output pin to assert. bit 5 motor enable 1 this bit controls the nmtr1 disk interface output. a logic ?1? in this bit will cause the output pin to assert. bit 6 motor enable 2 this bit controls the nmtr2 disk interface output. a logic ?1? in this bit will cause the output pin to assert. bit 7 motor enable 3 this bit controls the nmtr3 disk interface output. a logic ?1? in this bit will cause the output pin to assert.
34 table 13 ? fdc srb ? ps/2 model 30 mode 7 6 5 4 3 2 1 0 ndrv2 nds1 nds0 wdata f/f rdata f/f wgate f/f nds3 nds2 reset cond. n/a 1 1 0 0 0 1 1 table 1 4 - fdc dor 7 6 5 4 3 2 1 0 mot en3 mot en2 mot en1 mot en0 dmaen nreset drive sel1 drive sel0 reset cond. 0 0 0 0 0 0 0 0 bit 0 and 1 drive select these two bits are binary encoded for the two drive selects output pins nds0 and nds1, thereby allowing only one drive to be selected at one time. bit 2 nreset a logic ?0? written to this bit resets the fdc. this reset will remain active until a logic ?1? is written to this bit. this software reset does not affect the dsr and ccr registers, nor does it affect the other bits of the dor register. the minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset. bit 3 dmaen pc/at and model 30 mode: writing this bit to logic ?1? will enable the fdc?s ndack and tc inputs and enable the fdc?s drq and interrupt outputs. this bit being a logic ?0? will disable the fdc?s ndack and tc inputs, and hold the fdc?s drq and interrupt outputs in a high impedance state. this bit is a logic ?0? after a reset. ps/2 mode: in this mode the tc and the fdc?s drq, and interrupt pins are always enabled. during a reset, the drq, tc, and interrupt pins will remain enabled, but this bit will be cleared to a logic ?0?. bit 4 motor enable 0 this bit controls the disk interface output. a logic ?1? in this bit will cause the output pin to assert. bit 5 motor enable 1 this bit controls the nmtr1 disk interface output. a logic ?1? in this bit will cause the output pin to assert. bit 6 motor enable 2 this bit controls the nmtr2 disk interface output. a logic ?1? in this bit will cause the output pin to assert. bit 7 motor enable 3 this bit controls the nmtr3 disk interface output. a logic ?1? in this bit will cause the output pin to assert.
35 table 13 ? fdc internal 2 drive decode ? drives 0 and 1 swapped digital output register drive select outputs (active low) motor on outputs (active low) bit 7 bit 6 bit 5 bit 4 bit1 bit 0 nds1 nds0 nmtr1 nmtr0 x x x 1 0 0 0 1 nbit 4 nbit 5 x x 1 x 0 1 1 0 nbit 4 nbit 5 x 1 x x 1 0 1 1 nbit 4 nbit 5 1 x x x 1 1 1 1 nbit 4 nbit 5 0 0 0 0 x x 1 1 nbit 4 nbit 5 tape drive register (tdr) fdc i/o base address + 0x03 (read/write) this register is included for 82077 software compatability. the tdr is unaffected by a software reset. the improved data separator incorporates tape drive support and requires the tape select bits in the fdc tape drive register to identify which drive has been assigned to receive this support (see the following section). normal floppy mode normal mode. the tdr allows the user to assign tape support to a particular drive during initialization. any future references to that drive number automatically invokes tape support. the tape select bits are tdr[1:0]. the tdr register contains only bits 0 and 1. when this register is read, bits 2 ? 7 are a high impedance. table 14 - fdc tdr normal floppy mode db7 db6 db5 db4 db3 db2 db1 db0 reg 3f3 tri-state tri-state tri-state tri-state tri-state tri-state tape sel 1 tape sel 0 tape sel1 (tdr.1) tape sel2 (tdr.0) drive selected 0 0 none 0 1 1 1 0 2 1 1 3
36 enhanced floppy mode 2 (os2) the tdr register for enhanced floppy mode 2 operation. table 15 - fdc tdr enhanced floppy mode 2 (os2) db7 db6 db5 db4 db3 db2 db1 db0 reg 3f3 1 1 drive type id floppy boot drive tape sel1 tape sel0 bit 7 this bit is always set active high bit 6 this bit is always set active high bits 5 and 4 drive type id these bits reflect two of the bits of l0-crf1 (logical device 0 ? configuration register 0xf1). which two bits these are depends on the last drive selected in the digital output register. (see table 20 ) bits 3 and 2 floppy boot drive these bits reflect two of the bits of l0-crf1. bit 3 = l0-crf1-b7. bit 2 = l0-crf1-b6. bit 1 and 0 ? tape drive select (read/write) same as in normal and enhanced floppy mode 2. table 16 ? drive type id digital output register tdr register ? drive type id bit 1 bit 0 bit 5 bit 4 0 0 l0-crf2 ? b1 l0-crf2 ? b0 0 1 l0-crf2 ? b3 l0-crf2 ? b2 1 0 l0-crf2 ? b5 l0-crf2 ? b4 1 1 l0-crf2 ? b7 l0-crf2 ? b6 note: l0-crf2-bx = logical device 0, configuration register f2, bit x. mid[1:0] fdd interface pins the fdc media id pins are not supported in the FDC37N972. the mid[1:0] inputs to the fdc core are strapped so that the media id bits the tdr are always ?high?.
37 data rate select register (dsr) fdc i/o base address + 0x04 (write only) this register is write only. it is used to program the data rate, amount of write precompensation, power down status, and software reset. the data rate is programmed using the configuration control register (ccr) not the dsr, for pc/at and ps/2 model 30 and microchannel applications. other applications can set the data rate in the dsr. the data rate of the floppy controller is the most recent write of either the dsr or ccr. the dsr is unaffected by a software reset. a hardware reset will set the dsr to 02h, which corresponds to the default precompensation setting and 250 kbps. table 17 - fdc dsr 7 6 5 4 3 2 1 0 s/w reset power down 0 pre- comp2 pre- comp1 pre- comp0 drate sel1 drate sel0 reset cond. 0 0 0 0 0 0 1 0 bits 0 - 1 data rate select these bits control the data rate of the floppy controller. see table 19 for the settings corresponding to the individual data rates. the data rate select bits are unaffected by a software reset and are set to 250 kbps after a hardware reset. bits 2 - 4 precompensation select these three bits select the value of write precompensation that will be applied to the wdata output signal. table 18 shows the precompensation values for the combination of these bits settings. track 0 is the default starting track number to start precompensation. this starting track number can be changed by the configure command. bit 5 undefined should be written as a logic "0". bit 6 low power a logic "1" written to this bit will put the floppy controller into manual low power mode. the floppy controller clock and data separator circuits will be turned off. the controller will come out of manual low power mode after a software reset or access to the data register or main status register. bit 7 software reset this active high bit has the same function as the dor reset (dor bit 2) except that this bit is self clearing.
38 table 18 - fdc precompensation delays precomp 432 precompensation delay (nsec) <2mbps 2mbps 111 001 010 011 100 101 110 000 0.00 41.67 83.34 125.00 166.67 208.33 250.00 default 0 20.8 41.7 62.5 83.3 104.2 125 default default: see table 16 table 19 ? fdc data rates drive rate data rate data rate densel drate(1) drt1 drt0 sel1 sel0 mfm fm 1 0 0 0 1 1 1meg --- 1 1 1 0 0 0 0 500 250 1 0 0 0 0 0 1 300 150 0 0 1 0 0 1 0 250 125 0 1 0 0 1 1 1 1meg --- 1 1 1 0 1 0 0 500 250 1 0 0 0 1 0 1 500 250 0 0 1 0 1 1 0 250 125 0 1 0 1 0 1 1 1meg --- 1 1 1 1 0 0 0 500 250 1 0 0 1 0 0 1 2meg --- 0 0 1 1 0 1 0 250 125 0 1 0 drive rate table (recommended) 00 = 360k, 1.2m, 720k, 1.44m and 2.88m vertical format 01 = 3-mode drive 10 = 2 meg tape note 1: the drate and densel values are mapp ed onto the driveden pins.
39 table 20 - fdc drvden mapping dt1 dt0 drvden1 (1) drvden0 (1) drive type 0 0 drate0 densel 4/2/1 mb 3.5" 2/1 mb 5.25" fdds 2/1.6/1 mb 3.5" (3-mode) 1 0 drate0 drate1 0 1 drate0 ndensel ps/2 1 1 drate1 drate0 table 21 - fdc default precompensation delays data rate precompensation delays 2 mbps 1 mbps 500 kbps 300 kbps 250 kbps 20.8 ns 41.67 ns 125 ns 125 ns 125 ns
40 main status register fdc i/o base address + 0x04 (read only) the main status register is a read-only register and indicates the status of the disk controller. the main status register can be read at any time. the msr indicates when the disk controller is ready to receive data via the data register. it should be read before each byte transferring to or from the data register except in dma mode. no delay is required when reading the msr after a data transfer. table 22 - fdc msr 7 6 5 4 3 2 1 0 rqm dio non dma cmd busy drv3 busy drv2 busy drv1 busy drv0 busy bit 0 - 3 drvx busy these bits are set to 1s when a drive is in the seek portion of a command, including implied and overlapped seeks and recalibrates. bit 4 command busy this bit is set to a ?1? when a command is in progress. this bit will go active after the command byte has been accepted and goes inactive at the end of the results phase. if there is no result phase (seek, recalibrate commands), this bit is returned to a ?0? after the last command byte. bit 5 non-dma this mode is selected in the specify command and will be set to a ?1? during the execution phase of a command. this is for polled data transfers and helps differentiate between the data transfer phase and the reading of result bytes. bit 6 dio indicates the direction of a data transfer once a rqm is set. a ?1? indicates a read and a ?0? indicates a write is required. bit 7 rqm indicates that the host can transfer data if set to a ?1?. no access is permitted if set to a ?0?.
41 data register (fifo) fdc i/o base address + 0x05 (read/write) all command parameter information, disk data and result status are transferred between the host processor and the fdc through the data register. data transfers are governed by the rqm and dio bits in the main status register. the data register defaults to fifo disabled mode after any form of reset. this maintains pc/at hardware compatibility. the default values can be changed through the configure command (enable full fifo operation with threshold control). the advantage of the fifo is that it allows the system a larger dma latency without causing a disk error. table 31 gives several examples of the delays with a fifo. the data is based upon the following formula: threshold # x [8/data rate] - 1.5ms = delay at the start of a command, the fifo action is always disabled and command parameters must be sent based upon the rqm and dio bit settings. as the command execution phase is entered, the fifo is cleared of any data to ensure that invalid data is not transferred. an overrun or underrun will terminate the current command and the transfer of data. disk writes will complete the current sector by generating a 00 pattern and valid crc. reads require the host to remove the remaining data so that the result phase may be entered. table 23 - fifo service delay fifo threshold examples maximum delay to servicing at 2 mbps* data rate 1 byte 2 bytes 8 bytes 15 bytes 1 x 4 ms - 1.5 ms = 2.5 ms 2 x 4 ms - 1.5 ms = 6.5 ms 8 x 4 ms - 1.5 ms = 30.5 ms 15 x 4 ms - 1.5 ms = 58.5 ms fifo threshold examples maximum delay to servicing at 1 mbps data rate 1 byte 2 bytes 8 bytes 15 bytes 1 x 8 ms - 1.5 ms = 6.5 ms 2 x 8 ms - 1.5 ms = 14.5 ms 8 x 8 ms - 1.5 ms = 62.5 ms 15 x 8 ms - 1.5 ms = 118.5 ms fifo threshold examples maximum delay to servicing at 500 kbps data rate 1 byte 2 bytes 8 bytes 15 bytes 1 x 16 ms - 1.5 ms = 14.5 ms 2 x 16 ms - 1.5 ms = 30.5 ms 8 x 16 ms - 1.5 ms = 126.5 ms 15 x 16 ms - 1.5 ms = 238.5 ms
42 digital input register (dir) fdc i/o base address + 0x07 (read only) this register is read-only in all modes. dir - pc-at mode table 24 - fdc dir all modes 7 6 5 4 3 2 1 0 dsk chg reset cond. n/a n/a n/a n/a n/a n/a n/a n/a bit 0 ? 6 undefined the data bus outputs d0 ? 6 will remain in a high impedance state during a read of this register. bit 7 dskchg this bit monitors the pin of the same name and reflects the opposite value seen on the disk cable. dir ? ps/2 mode table 25 - fdc dir ps/2 mode 7 6 5 4 3 2 1 0 dsk chg 1 1 1 1 drate sel1 drate sel0 nhigh dens reset cond. n/a n/a n/a n/a n/a n/a n/a 1 bit 0 nhigh dens this bit is low whenever the 500 kbps or 1 mbps data rates are selected, and high when 250 kbps and 300 kbps are selected. bits 1 ? 2 data rate select these bits control the data rate of the floppy controller. see table 19 for the settings corresponding to the individual data rates. the data rate select bits are unaffected by a software reset, and are set to 250 kbps after a hardware reset. bits 3 ? 6 undefined always read as a logic ?1? bit 7 dskchg this bit monitors the pin of the same name and reflects the opposite value seen on the disk cable.
43 dir ? model 30 mode table 26 - fdc dir model 30 mode 7 6 5 4 3 2 1 0 dsk chg 0 0 0 dmaen noprec drate sel1 drate sel0 reset cond. n/a 0 0 0 0 0 1 0 bits 0 and 1 data rate select these bits control the data rate of the floppy controller. see table 19 for the settings corresponding to the individual data rates. the data rate select bits are unaffected by a software reset and are set to 250 kbps after a hardware reset. bit 2 noprec this bit reflects the value of noprec bit set in the ccr register. bit 3 dmaen this bit reflects the value of dmaen bit set in the dor register bit 3. bits 4 - 6 undefined always read as a logic "0" bit 7 dskchg this bit monitors the pin of the same name and reflects the opposite value seen on the pin. configuration control register (ccr) fdc i/o base address + 0x07 (write only) table 27 - fdc ccr pc/at and ps/2 mode 7 6 5 4 3 2 1 0 drate sel1 drate sel0 reset cond. n/a n/a n/a n/a n/a n/a 1 0 bit 0 and 1 data rate select 0 and 1 these bits determine the data rate of the floppy controller. see table 19 for the appropriate values. bit 2 - 7 reserved should be set to a logical "0"
44 table 28 - fdc ccr - ps/2 model 30 mode 7 6 5 4 3 2 1 0 noprec drate sel1 drate sel0 reset cond. n/a n/a n/a n/a n/a n/a 1 0 bit 0 and 1 data rate select 0 and 1 these bits determine the data rate of the floppy controller. see table 19 for the appropriate values. bit 2 no precompensation this bit can be set by software, but it has no functionality. it can be read by bit 2 of the dsr when in model 30 register mode. unaffected by software reset. bit 3 - 7 reserved should be set to a logical "0". table 19 shows the state of the densel pin. the densel pin is set high after a hardware reset and is unaffected by the dor and the dsr resets. status register encoding during the result phase of certain commands, the data register contains data bytes that give the status of the command just executed. table 29 - fdc status register 0 bit no. symbol name description 7,6 ic interrupt code 00 - normal termination of command. the specified command was properly executed and completed without error. 01 - abnormal termination of command. command execution was started, but was not successfully completed. 10 - invalid command. the requested command could not be executed. 11 - abnormal termination caused by polling. 5 se seek end the fdc completed a seek, relative seek or recalibrate command (used during a sense interrupt command). 4 ec equipment check the trk0 pin failed to become a "1" after: step pulses in the recalibrate command. the relative seek command caused the fdc to step outward beyond track 0. 3 unused. this bit is always "0". 2 h head address the current head address. 1,0 ds1,0 drive select the current selected drive.
45 table 30 - fdc status register 1 bit no. symbol name description 7 en end of cylinder the fdc tried to access a sector beyond the final sector of the track (255d). will be set if tc is not issued after read or write data command. 6 unused. this bit is always "0". 5 de data error the fdc detected a crc error in either the id field or the data field of a sector. 4 or overrun/ underrun becomes set if the fdc does not receive cpu or dma service within the required time interval, resulting in data overrun or underrun. 3 unused. this bit is always "0". 2 nd no data any one of the following: read data, read deleted data command - the fdc did not find the specified sector. read id command - the fdc cannot read the id field without an error. read a track command - the fdc cannot find the proper sector sequence. 1 nw not writable wp pin became a "1" while the fdc is executing a write data, write deleted data, or format a track command. 0 ma missing address mark any one of the following: the fdc did not detect an id address mark at the specified track after encountering the index pulse from the idx pin twice. the fdc cannot detect a data address mark or a deleted data address mark on the specified track.
46 table 31 - fdc status register 2 bit no. symbol name description 7 unused. this bit is always "0". 6 cm control mark any one of the following: read data command - the fdc encountered a deleted data address mark. read deleted data command - the fdc encountered a data address mark. 5 dd data error in data field the fdc detected a crc error in the data field. 4 wc wrong cylinder the track address from the sector id field is different from the track address maintained inside the fdc. 3 unused. this bit is always "0". 2 unused. this bit is always "0". 1 bc bad cylinder the track address from the sector id field is different from the track address maintained inside the fdc and is equal to ff hex, which indicates a bad track with a hard error according to the ibm soft-sectored format. 0 md missing data address mark the fdc cannot detect a data address mark or a deleted data address mark. table 32 - fdc status register 3 bit no. symbol name description 7 u nused . t his bit is always "0". 6 wp write protected indicates the status of the wp pin. 5 unused. this bit is always "1". 4 t0 track 0 indicates the status of the trk0 pin. 3 unused. this bit is always "1". 2 hd head address indicates the status of the hdsel pin. 1,0 ds1,0 drive select indicates the status of the nds1, nds0 pins. fdc reset there are three sources of system reset on the fdc: the nreset_out bit of the 8051?s output enable register (which controls the nreset_out pin of the FDC37N972); a reset generated via a bit in the dor; and a reset generated via a bit in the dsr. at vcc2 power on, a vcc2 power on reset initializes the fdc. all resets take the fdc out of the power down state. all operations are terminated upon a reset, and the floppy disk controller enters an idle state. a reset while a disk write is in progress will corrupt the data and crc. on exiting the reset state, various internal registers are cleared, including the configure command information, and the floppy disk controller waits for a new command. drive polling will start unless disabled by a new configure command.
47 nreset_ out pin (hardware reset) the nreset_out pin is a global reset and clears all registers except those programmed by the specify command. the dor reset bit is enabled and must be cleared by the host to exit the reset state. dor reset vs. dsr reset (software reset) these two resets are functionally the same. both will reset the fdc core, which affects drive status information and the fifo circuits. the dsr reset clears itself automatically while the dor reset requires the host to manually clear it. dor reset has precedence over the dsr reset. the dor reset is set automatically upon a nreset_out pin reset. the user must manually clear this reset bit in the dor to exit the reset state. fdc modes of operation the fdc has three modes of operation, pc/at mode, ps/2 mode and model 30 mode. these are determined by the state of ident and mfm, bits[3] and [2] respectively of l0-crf0. pc/at mode - (ident high, mfm a "don't care") the pc/at register set is enabled, the dma enable bit of the dor becomes valid (the fdc?s irq and drq can be hi-z), and tc and densel become active high signals. ps/2 mode - (ident low, mfm high) this mode supports the ps/2 models 50/60/80 configuration and register set. the dma bit of the dor becomes a "don't care", (the fdc?s irq and drq are always valid), tc and densel become active low. model 30 mode - (ident low, mfm low) this mode supports ps/2 model 30 configuration and register set. the dma enable bit of the dor becomes valid (the fdc?s irq and drq can be hi-z), tc is active high and densel is active low. dma transfers dma transfers are enabled with the specify command and are initiated by the fdc by activating its drq pin during a data transfer command. the fifo is enabled directly by asserting ndack and addresses need not be valid. note that if the dma controller (i.e. 8237a) is programmed to function in verify mode, a pseudo read is performed by the fdc based only on ndack. this mode is only available when the fdc has been configured into byte mode (fifo disabled) and is programmed to do a read. with the fifo enabled, the fdc can perform the above operation by using the verify command; no dma operation is needed. controller phases for simplicity, command handling in the fdc can be divided into three phases: command, execution, and result. each phase is described in the following sections. command phase after a reset, the fdc enters the command phase and is ready to accept a command from the host. for each of the commands, a defined set of command code bytes and parameter bytes has to be written to the fdc before the command phase is complete. (please refer to table 33 for the command set descriptions). these bytes of data must be transferred in the order prescribed. before writing to the fdc, the host must examine the rqm and dio bits of the main status register. rqm and dio must be equal to "1" and "0" respectively before command bytes may be written. rqm is set false by the fdc after each write cycle until the received
48 byte is processed. the fdc asserts rqm again to request each parameter byte of the command unless an illegal command condition is detected. after the last parameter byte is received, rqm remains "0" and the fdc automatically enters the next phase as defined by the command definition. the fifo is disabled during the command phase to provide for the proper handling of the "invalid command" condition. execution phase all data transfers to or from the fdc occur during the execution phase, which can proceed in dma or non-dma mode as indicated in the specify command. after a reset, the fifo is disabled. each data byte is transferred by an fdc irq or drq depending on the dma mode. the configure command can enable the fifo and set the fifo threshold value. the following paragraphs detail the operation of the fifo flow control. in these descriptions, is defined as the number of bytes available to the fdc when service is requested from the host and ranges from 1 to 16. the parameter fifothr, which the user programs, is one less and ranges from 0 to 15. a low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of the request for both read and write cases. the host reads (writes) from (to) the fifo until empty (full), then the transfer request goes inactive. the host must be very responsive to the service request. this is the desired case for use with a "fast" system. a high value of threshold (i.e. 12) is used with a "sluggish" system by affording a long latency period after a service request, but results in more frequent service requests. non-dma mode - transfers from the fifo to the host the fdc?s irq pin and rqm bits in the main status register are activated when the fifo contains (16-) bytes or the last bytes of a full sector have been placed in the fifo. the fdc?s irq pin can be used for interrupt- driven systems, and rqm can be used for polled systems. the host must respond to the request by reading data from the fifo. this process is repeated until the last byte is transferred out of the fifo. the fdc will deactivate the fdc?s irq pin and rqm bit when the fifo becomes empty. non-dma mode - transfers from the host to the fifo the fdc?s irq pin and rqm bit in the main status register are activated upon entering the execution phase of data transfer commands. the host must respond to the request by writing data into the fifo. the fdc?s irq pin and rqm bit remain true until the fifo becomes full. they are set true again when the fifo has bytes remaining in the fifo. the fdc?s irq pin will also be deactivated if tc and ndack both go inactive. the fdc enters the result phase after the last byte is taken by the fdc from the fifo (i.e. fifo empty condition). dma mode - transfers from the fifo to the host the fdc activates the fdc?s drq pin when the fifo contains (16 - ) bytes, or the last byte of a full sector transfer has been placed in the fifo. the dma controller must respond to the request by reading data from the fifo. the fdc will deactivate the fdc?s drq pin when the fifo becomes empty. fdc?s drq goes inactive after ndack goes active for the last byte of a data transfer (or on the active edge of nior, on the last byte, if no edge is present on ndack). a data underrun may
49 occur if the fdc?s drq is not removed in time to prevent an unwanted cycle. dma mode - transfers from the host to the fifo the fdc activates the fdc?s drq pin when entering the execution phase of the data transfer commands. the dma controller must respond by activating the ndack and niow pins placing data in the fifo. the fdc?s drq remains active until the fifo becomes full. the fdc?s drq is again set true when the fifo has bytes remaining in the fifo. the fdc will also deactivate the fdc?s drq pin when tc becomes true (qualified by ndack), indicating that no more data is required. the fdc?s drq goes inactive after ndack goes active for the last byte of a data transfer (or on the active edge of niow of the last byte, if no edge is present on ndack). a data overrun may occur if the fdc?s drq is not removed in time to prevent an unwanted cycle. data transfer termination the fdc supports terminal count explicitly through the tc pin and implicitly through the underrun/overrun and end-of-track (eot) functions. for full sector transfers, the eot parameter can define the last sector to be transferred in a single or multi-sector transfer. if the last sector to be transferred is a partial sector, the host can stop transferring the data in mid-sector, and the fdc will continue to complete the sector as if a hardware tc was received. the only difference between these implicit functions and tc is that they return "abnormal termination" result status. such status indications can be ignored if they were expected. note that when the host is sending data to the fifo of the fdc, the internal sector count will be complete when the fdc reads the last byte from its side of the fifo. there may be a delay in the removal of the transfer request signal of up to the time taken for the fdc to read the last 16 bytes from the fifo. the host must tolerate this delay. result phase the generation of the fdc?s irq determines the beginning of the result phase. for each of the commands, a defined set of result bytes has to be read from the fdc before the result phase is complete. these bytes of data must be read out for another command to start. rqm and dio must both equal "1" before the result bytes may be read. after all the result bytes have been read, the rqm and dio bits switch to "1" and "0" respectively, and the cb bit is cleared, indicating that the fdc is ready to accept the next command. command set/descriptions commands can be written whenever the fdc is in the command phase. each command has a unique set of needed parameters and status results. the fdc checks to see that the first byte is a valid command and, if valid, proceeds withthe command. if it is invalid, an interrupt is issued. the user sends a sense interrupt status command which returns an invalid command error. refer to table 33 for explanations of the various symbols used. table 34 lists the required parameters and the results associated with each command that the fdc is capable of performing.
50 ds1 ds0 drive 0 0 1 1 0 1 0 1 drive 0 drive 1 drive 2 drive 3 table 33 - description of the fdc command symbols symbol name description c cylinder address the currently selected address; 0 to 255. d data pattern the pattern to be written in each sector data field during formatting. d0, d1, d2, d3 drive select 0-3 designates which drives are perpendicular drives on the perpendicular mode command. a "1" indicates a perpendicular drive. dir direction control if this bit is 0, then the head will step out from the spindle during a relative seek. if set to a 1, the head will step in toward the spindle. ds0, ds1 disk drive select dtl special sector size by setting n to zero (00), dtl may be used to control the number of bytes transferred in disk read/write commands. the sector size (n = 0) is set to 128. if the actual sector (on the diskette) is larger than dtl, the remainder of the actual sector is read but is not passed to the host during read commands; during write commands, the remainder of the actual sector is written with all zero bytes. the crc check code is calculated with the actual sector. when n is not zero, dtl has no meaning and should be set to ff hex. ec enable count when this bit is "1" the "dtl" parameter of the verify command becomes sc (number of sectors per track). efifo enable fifo this active low bit when a 0, enables the fifo. a "1" disables the fifo (default). eis enable implied seek when set, a seek operation will be performed before executing any read or write command that requires the c parameter in the command phase. a "0" disables the implied seek. eot end of track the final sector number of the current track. gap alters gap 2 length when using perpendicular mode. gpl gap length the gap 3 size. (gap 3 is the space between sectors excluding the vco synchronization field). h/hds head address selected head: 0 or 1 (disk side 0 or 1) as encoded in the sector id field. hlt head load time the time interval that the fdc waits after loading the head and before initializing a read or write operation. refer to the specify command for actual delays.
51 symbol name description hut head unload time the time interval from the end of the execution phase (of a read or write command) until the head is unloaded. refer to the specify command for actual delays. lock lock defines whether efifo, fifothr, and pretrk parameters of the configure command can be reset to their default values by a "software reset". (a reset caused by writing to the appropriate bits of either tha dsr or dor) mfm mfm/fm mode selector a one selects the double density (mfm) mode. a zero selects single density (fm) mode. mt multi-track selector when set, this flag selects the multi-track operating mode. in this mode, the fdc treats a complete cylinder under head 0 and 1 as a single track. the fdc operates as this expanded track started at the first sector under head 0 and ended at the last sector under head 1. with this flag set, a multitrack read or write operation will automatically continue to the first sector under head 1 when the fdc finishes operating on the last sector under head 0. n sector size code this specifies the number of bytes in a sector. if this parameter is "00", then the sector size is 128 bytes. the number of bytes transferred is determined by the dtl parameter. otherwise the sector size is (2 raised to the "n'th" power) times 128. all values up to "07" hex are allowable. "07"h would equal a sector size of 16k. it is the user's responsibility to not select combinations that are not possible with the drive. n sector size 128 bytes 256 bytes 512 bytes 1024 bytes ... ... 07 16 kbytes ncn new cylinder number the desired cylinder number. nd non-dma mode flag when set to 1, indicates that the fdc is to operate in the non- dma mode. in this mode, the host is interrupted for each data transfer. when set to 0, the fdc operates in dma mode, interfacing to a dma controller by means of the drq and ndack signals. ow overwrite the bits d0-d3 of the perpendicular mode command can only be modified if ow is set to 1. ow id defined in the lock command. pcn present cylinder number the current position of the head at the completion of sense interrupt status command. poll polling disable when set, the internal polling routine is disabled. when clear, polling is enabled.
52 symbol name description pretrk precompensation start track number programmable from track 00 to ffh. r sector address the sector number to be read or written. in multi-sector transfers, this parameter specifies the sector number of the first sector to be read or written. rcn relative cylinder number relative cylinder offset from present cylinder as used by the relative seek command. sc number of sectors per track the number of sectors per track to be initialized by the format command. the number of sectors per track to be verified during a verify command when ec is set. sk skip flag when set to 1, sectors containing a deleted data address mark will automatically be skipped during the execution of read data. if read deleted is executed, only sectors with a deleted address mark will be accessed. when set to "0", the sector is read or written the same as the read and write commands. srt step rate interval the time interval between step pulses issued by the fdc. programmable from 0.5 to 8 milliseconds in increments of 0.5 ms at the 1 mbit data rate. refer to the specify command for actual delays. st0 st1 st2 st3 status 0 status 1 status 2 status 3 registers within the fdc which store status information after a command has been executed. this status information is available to the host during the result phase after command execution. wgate write gate alters timing of we to allow for pre-erase loads in perpendicular drives.
53 fdc instruction set table 34 - fdc instruction set read data data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm sk 0 0 1 1 0 command codes w 0 0 0 0 0 hds ds1 ds0 w -------- c -------- sector id information prior to command execution. w -------- h -------- w -------- r -------- w -------- n -------- w ------- eot ------- w ------- gpl ------- w ------- dtl ------- execution data transfer between the fdd and system. result r ------- st0 ------- status information after com mand execution. r ------- st1 ------- r ------- st2 ------- r -------- c -------- sector id information after com mand execution. r -------- h -------- r -------- r -------- r -------- n --------
54 read deleted data data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm sk 0 1 1 0 0 command codes w 0 0 0 0 0 hds ds1 ds0 w -------- c -------- sector id information prior to command execution. w -------- h -------- w -------- r -------- w -------- n -------- w ------- eot ------- w ------- gpl ------- w ------- dtl ------- execution data transfer between the fdd and system. data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks r ------- st2 ------- r -------- c -------- sector id information after com mand execution. r -------- h -------- r -------- r -------- r -------- n --------
55 write data data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm 0 0 0 1 0 1 command codes w 0 0 0 0 0 hds ds1 ds0 w -------- c -------- sector id information prior to command execution. w -------- h -------- w -------- r -------- w -------- n -------- w ------- eot ------- w ------- gpl ------- w ------- dtl ------- execution data transfer between the fdd and system. result r ------- st0 ------- status information after com mand execution. r ------- st1 ------- r ------- st2 ------- r -------- c -------- sector id information after command execution. r -------- h -------- r -------- r -------- r -------- n --------
56 write deleted data data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm 0 0 1 0 0 1 command codes w 0 0 0 0 0 hds ds1 ds0 w -------- c -------- sector id information prior to command execution. w -------- h -------- w -------- r -------- w -------- n -------- w ------- eot ------- w ------- gpl ------- w ------- dtl ------- execution data transfer between the fdd and system. result r ------- st0 ------- status information after com mand execution. r ------- st1 ------- r ------- st2 ------- r -------- c -------- sector id information after command execution. r -------- h -------- r -------- r -------- r -------- n --------
57 read a track data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 mfm 0 0 0 0 1 0 command codes w 0 0 0 0 0 hds ds1 ds0 w -------- c -------- sector id information prior to command execution. w -------- h -------- w -------- r -------- w -------- n -------- w ------- eot ------- w ------- gpl ------- w ------- dtl ------- data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks r ------- st1 ------- r ------- st2 ------- r -------- c -------- sector id information after command execution. r -------- h -------- r -------- r -------- r -------- n --------
58 verify data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w mt mfm sk 1 0 1 1 0 command codes w ec 0 0 0 0 hds ds1 ds0 w -------- c -------- sector id information prior to command execution. w -------- h -------- w -------- r -------- w -------- n -------- w ------- eot ------- w ------- gpl ------- w ------ dtl/sc ------ execution no data transfer takes place. result r ------- st0 ------- status information after com mand execution. r ------- st1 ------- r ------- st2 ------- r -------- c -------- sector id information after command execution. r -------- h -------- r -------- r -------- r -------- n --------
59 version data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 1 0 0 0 0 command code result r 1 0 0 1 0 0 0 0 enhanced controller format a track data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 mfm 0 0 1 1 0 1 command codes w 0 0 0 0 0 hds ds1 ds0 w -------- n -------- bytes/sector w -------- sc -------- sectors/cylinder w ------- gpl ------- gap 3 w -------- d -------- filler byte execution for each sector repeat: w -------- c -------- input sector parameters w -------- h -------- w -------- r -------- w -------- n -------- fdc formats an entire cylinder result r ------- st0 ------- status information after command execution r ------- st1 ------- r ------- st2 ------- r ------ undefined ------ r ------ undefined ------ r ------ undefined ------ r ------ undefined ------
60 recalibrate data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 0 1 1 1 command codes w 0 0 0 0 0 0 ds1 ds0 execution head retracted to track 0 interrupt. sense interrupt status data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 1 0 0 0 command codes result r ------- st0 ------- status information at the end of each seek operation. r ------- pcn ------- specify data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 0 0 1 1 command codes w --- srt --- --- hut --- w ------ hlt ------ nd sense drive status data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 0 1 0 0 command codes w 0 0 0 0 0 hds ds1 ds0 result r ------- st3 ------- status information about fdd seek data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 1 1 1 1 command codes w 0 0 0 0 0 hds ds1 ds0 w ------- ncn ------- execution head positioned over proper cylinder on diskette.
61 configure data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 1 0 0 1 1 configure information w 0 0 0 0 0 0 0 0 w 0 eis efifo poll --- fifothr --- execution w --------- pretrk --------- relative seek data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 1 dir 0 0 1 1 1 1 w 0 0 0 0 0 hds ds1 ds0 w ------- rcn ------- dumpreg data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 0 1 1 1 0 *note: registers placed in fifo execution result r ------ pcn-drive 0 ------- r ------ pcn-drive 1 ------- r ------ pcn-drive 2 ------- r ------ pcn-drive 3 ------- r ---- srt ---- --- hut --- r ------- hlt ------- nd r ------- sc/eot ------- r lock 0 d3 d2 d1 d0 gap wgate r 0 eis efifo poll -- fifothr -- r -------- pretrk --------
62 read id data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 mfm 0 0 1 0 1 0 commands w 0 0 0 0 0 hds ds1 ds0 execution the first correct id information on the cylinder is stored in data register result r -------- st0 -------- status information after command execution. disk status after the command has completed r -------- st1 -------- r -------- st2 -------- r -------- c -------- r -------- h -------- r -------- r -------- r -------- n -------- perpendicular mode data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 0 0 1 0 0 1 0 command codes ow 0 d3 d2 d1 d0 gap wgate
63 invalid codes data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w ----- invalid codes ----- invalid command codes (noop - fdc goes into stand by state) result r ------- st0 ------- st0 = 80h lock data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w lock 0 0 1 0 1 0 0 command codes result r 0 0 0 lock 0 0 0 0 sc is returned if the last command that was issued was the format command. eot is returned if the last command was a read or write. note: these bits are used internally only. they are not reflected in the drive select pins. it is the user's responsibility to maintain correspondence between these bits and the drive select pins (dor).
64 fdc data transfer commands all of the read data, write data and verify type commands use the same parameter bytes and return the same results information, the only difference being the coding of bits 0-4 in the first byte. an implied seek will be executed if the feature was enabled by the configure command. this seek is completely transparent to the user. the drive busy bit for the drive will go active in the main status register during the seek portion of the command. if the seek portion fails, it will be reflected in the results status normally returned for a read/write data command. status register 0 (st0) would contain the error code and c would contain the cylinder on which the seek failed. table 35 - fdc sector sizes n sector size 00 01 02 03 .. 07 128 bytes 256 bytes 512 bytes 1024 bytes ... 16 kbytes read data a set of nine (9) bytes is required to place the fdc in the read data mode. after the read data command has been issued, the fdc loads the head (if it is in the unloaded state), waits the specified head settling time (defined in the specify command), and begins reading id address marks and id fields. when the sector address read off the diskette matches with the sector address specified in the command, the fdc reads the sector's data field and transfers the data to the fifo. after completion of the read operation from the current sector, the sector address is incremented by one and the data from the next logical sector is read and output via the fifo. this continuous read function is called "multi- sector read operation". upon receipt of tc, or an implied tc (fifo overrun/underrun), the fdc stops sending data but will continue to read data from the current sector, check the crc bytes, and at the end of the sector, terminate the read data command. n determines the number of bytes per sector (see table 35 above). if n is set to zero, the sector size is set to 128. the dtl value determines the number of bytes to be transferred. if dtl is less than 128, the fdc transfers the specified number of bytes to the host. for reads, it continues to read the entire 128-byte sector and checks for crc errors. for writes, it completes the 128-byte sector by filling in zeros. if n is not set to 00 hex, dtl should be set to ff hex and has no impact on the number of bytes transferred. the amount of data which can be handled with a single command to the fdc depends upon mt (multi-track) and n (number of bytes/sector). the multi-track function (mt) allows the fdc to read data from both sides of the diskette. for a particular cylinder, data will be transferred starting at sector 1, side 0 and completing the last sector of the same track at side 1.
65 if the host terminates a read or write operation in the fdc, the id information in the result phase is dependent upon the state of the mt bit and eot byte. at the completion of the read data command, the head is not unloaded until after the head unload time interval (specified in the specify command) has elapsed. if the host issues another command before the head unloads, then the head settling time may be saved between subsequent reads. if the fdc detects a pulse on the nindex pin twice without finding the specified sector (meaning that the diskette's index hole passes through index detect logic in the drive twice), the fdc sets the ic code in status register 0 to "01" indicating abnormal termination, sets the nd bit in status register 1 to "1" indicating a sector not found, and terminates the read data command. after reading the id and data fields in each sector, the fdc checks the crc bytes. ifa crc error occurs in the id or data field, the fdc sets the ic code in status register 0 to "01" indicating abnormal termination, sets the de bit flag in status register 1 to "1", sets the dd bit in status register 2 to "1" if crc is incorrect in the id field, and terminates the read data command. table 40 - verify command result phase table describes the effect of the sk bit on the read data command execution and results. except where noted in table 36 , the c or r value of the sector address is automatically incremented (see table 42 ). table 36 - effects of mt and n bits mt n maximum transfer capacity final sector read from disk 0 1 0 1 0 1 1 1 2 2 3 3 256 x 26 = 6,656 256 x 52 = 13,312 512 x 15 = 7,680 512 x 30 = 15,360 1024 x 8 = 8,192 1024 x 16 = 16,384 26 at side 0 or 1 26 at side 1 15 at side 0 or 1 15 at side 1 8 at side 0 or 1 16 at side 1 table 37 - skip bit vs read data command sk bit value data address mark type encountered results sector read? cm bit of st2 set? description of results 0 normal data yes no normal termination 1 deleted data no yes normal termination. sector not read ("skipped")
66 read deleted data this command is the same as the read data command, only it operates on sectors that contain a deleted data address mark at the beginning of a data field. table 41 describes the effect of the sk bit on the read deleted data command execution and results. except where noted in table 41 , the c or r value of the sector address is automatically incremented (see table 42 ). table 38 - skip bit vs. read deleted data command sk bit value data address mark type encountered results sector read? cm bit of st2 set? description of results 0 normal data yes yes address not incremented. next sector not searched for 0 deleted data yes no normal termination 1 normal data no yes normal termination. sector not read ("skipped") 1 deleted data yes no normal termination
67 read a track this command is similar to the read data command except that the entire data field is read continuously from each of the sectors of a track. immediately after encountering a pulse on the nindex pin, the fdc starts to read all data fields on the track as continuous blocks of data without regard to logical sector numbers. if the fdc finds an error in the id or data crc check bytes, it continues to read data from the track and sets the appropriate error bits at the end of the command. the fdc compares the id information read from each sector with the specified value in the command and sets the nd flag of status register 1 to a "1" if there is no comparison. multi-track or skip operations are not allowed with this command. the mt and sk bits (bits d7 and d5 of the first command byte respectively) should always be set to "0". this command terminates when the eot specified number of sectors has not been read. if the fdc does not find an id address mark on the diskette after the second occurrence of a pulse on the idx pin, then it sets the ic code in status register 0 to "01" (abnormal termination), sets the ma bit in status register 1 to "1", and terminates the command. table 39 - result phase table mt head final sector transferred to host id information at result phase c h r n 0 0 less than eot nc nc r + 1 nc equal to eot c + 1 nc 01 nc 1 less than eot nc nc r + 1 nc equal to eot c + 1 nc 01 nc 1 0 less than eot nc nc r + 1 nc equal to eot nc lsb 01 nc 1 less than eot nc nc r + 1 nc equal to eot c + 1 lsb 01 nc nc: no change, the same value as the one at the beginning of command execution. lsb: least significant bit, the lsb of h is complemented.
68 write data after the write data command has been issued, the fdc loads the head (if it is in the unloaded state), waits the specified head load time if unloaded (defined in the specify command), and begins reading id fields. when the sector address read from the diskette matches the sector address specified in the command, the fdc reads the data from the host via the fifo and writes it to the sector's data field. after writing data into the current sector, the fdc computes the crc value and writes it into the crc field at the end of the sector transfer. the sector number stored in "r" is incremented by one, and the fdc continues writing to the next data field. the fdc continues this "multi-sector write operation". upon receipt of a terminal count signal or if a fifo over/under run occurs while a data field is being written, then the remainder of the data field is filled with zeros. the fdc reads the id field of each sector and checks the crc bytes. if it detects a crc error in one of the id fields, it sets the ic code in status register 0 to "01" (abnormal termination), sets the de bit of status register 1 to "1", and terminates the write data command. the write data command operates in much the same manner as the read data command. the following items are the same. please refer to the read data command for details: transfer capacity en (end of cylinder) bit nd (no data) bit head load, unload time interval id information when the host terminates the command definition of dtl when n = 0 and when n does not = 0. write deleted data this command is almost the same as the write data command except that a deleted data address mark is written at the beginning of the data field instead of the normal data address mark. this command is typically used to mark a bad sector containing an error on the floppy disk. verify the verify command is used to verify the data stored on a disk. this command acts exactly like a read data command except that no data is transferred to the host. data is read from the disk and crc is computed and checked against the previously-stored value. because data is not transferred to the host, tc (pin 94) cannot be used to terminate this command. by setting the ec bit to "1", an implicit tc will be issued to the fdc. this implicit tc will occur when the sc value has decremented to 0 (an sc value of 0 will verify 256 sectors). this command can also be terminated by setting the ec bit to "0" and the eot value equal to the final sector to be checked. if ec is set to "0", dtl/sc should be programmed to 0ffh. refer to table 42 and table 43 for information concerning the values of mt and ec versus sc and eot value.
69 definitions: # sectors per side = number of formatted sectors per each side of the disk. # sectors remaining = number of formatted sectors left which can be read, including side 1 of the disk if mt is set to "1". table 40 - verify command result phase table mt ec sc/eot value termination result 0 0 sc = dtl eot # sectors per side success termination result phase valid 0 0 sc = dtl eot > # sectors per side unsuccessful termination result phase invalid 0 1 sc # sectors remaining and eot # sectors per side successful termination result phase valid 0 1 sc > # sectors remaining or eot > # sectors per side unsuccessful termination result phase invalid 1 0 sc = dtl eot # sectors per side successful termination result phase valid 1 0 sc = dtl eot > # sectors per side unsuccessful termination result phase invalid 1 1 sc # sectors remaining and eot # sectors per side successful termination result phase valid 1 1 sc > # sectors remaining or eot > # sectors per side unsuccessful termination result phase invalid note: if mt is set to "1" and the sc value is greater than the number of remaining formatted sectors on side 0, verifying will continue on side 1 of the disk. format a track the format command allows an entire track to be formatted. after a pulse from the idx pin is detected, the fdc starts writing data on the disk including gaps, address marks, id fields, and data fields per the ibm system 34 or 3740 format (mfm or fm respectively). the particular values that will be written to the gap and data field are controlled by the values programmed into n, sc, gpl, and d which are specified by the host during the command phase. the data field of the sector is filled with the data byte specified by d. the id field for each sector is supplied by the host; that is, four data bytes per sector are needed by the fdc for c, h, r, and n (cylinder, head, sector number and sector size respectively). after formatting each sector, the host must send new values for c, h, r and n to the fdc for the next sector on the track. the r value (sector number) is the only value that must be changed by the host after each sector is formatted. this allows the disk to be formatted with nonsequential sector addresses (interleaving). this incrementing and formatting continues for the whole track until the fdc encounters a pulse on the idx pin again and it terminates the command.
70 table 45 contains typical values for gap fields which are dependent upon the size of the sector and the number of sectors on each track. actual values can vary due to drive electronics. table 41 - diskette format fields system 34 (double density) format gap4a 80x 4e sync 12x 00 iam gap1 50x 4e sync 12x 00 idam c y l h d s e c n o c r c gap2 22x 4e sync 12x 00 data am data c r c gap3 gap 4b 3x c2 fc 3x a1 fe 3x a1 fb f8 system 3740 (single density) format gap4a 40x ff sync 6x 00 iam gap1 26x ff sync 6x 00 idam c y l h d s e c n o c r c gap2 11x ff sync 6x 00 data am data c r c gap3 gap 4b fc fe fb or f8 perpendicular format gap4a 80x 4e sync 12x 00 iam gap1 50x 4e sync 12x 00 idam c y l h d s e c n o c r c gap2 41x 4e sync 12x 00 data am data c r c gap3 gap 4b 3x c2 fc 3x a1 fe 3x a1 fb f8
71 table 42 - typical values for formatting format sector size n sc gpl1 gpl2 5.25" drives fm 128 128 512 1024 2048 4096 00 00 02 03 04 05 12 10 08 04 02 01 07 10 18 46 c8 c8 09 19 30 87 ff ff mfm 256 256 512* 1024 2048 4096 01 01 02 03 04 05 12 10 09 04 02 01 0a 20 2a 80 c8 c8 0c 32 50 f0 ff ff 3.5" drives fm 128 256 512 0 1 2 0f 09 05 07 0f 1b 1b 2a 3a mfm 256 512** 1024 1 2 3 0f 09 05 0e 1b 35 36 54 74 gpl1 = suggested gpl values in read and write commands to avoid splice point between data field and id field of contiguous sections. gpl2 = suggested gpl value in format a track command. *pc/at values (typical) **ps/2 values (typical). applies with 1.0 mb and 2.0 mb drives. note: all values except sector size are in hex. fdc control commands control commands differ from the other commands in that no data transfer takes place. three commands generate an interrupt when complete: read id, recalibrate, and seek. the other control commands do not generate an interrupt. read id the read id command is used to find the present position of the recording heads. the fdc stores the values from the first id field it is able to read into its registers. if the fdc does not find an id address mark on the diskette after the second occurrence of a pulse on the nindex pin, it then sets the ic code in status register 0 to "01" (abnormal termination), sets the ma bit in status register 1 to "1", and terminates the command. the following commands will generate an interrupt upon completion. they do not return any result bytes. it is highly recommended that control commands be followed by the sense interrupt status command. otherwise, valuable interrupt status information will be lost. recalibrate this command causes the read/write head within the fdc to retract to the track 0 position. the fdc clears the contents of the pcn counter
72 and checks the status of the ntr0 pin from the fdd. as long as the ntr0 pin is low, the dir pin remains 0 and step pulses are issued. when the ntr0 pin goes high, the se bit in status register 0 is set to "1" and the command is terminated. if the ntr0 pin is still low after 79 step pulses have been issued, the fdc sets the se and the ec bits of status register 0 to "1" and terminates the command. disks capable of handling more than 80 tracks per side may require more than one recalibrate command to return the head back to physical track 0. the recalibrate command does not have a result phase. the sense interrupt status command must be issued after the recalibrate command to effectively terminate it and to provide verification of the head position (pcn). during the command phase of the recalibrate operation, the fdc is in the busy state, but during the execution phase it is in a non-busy state. at this time, another recalibrate command may be issued, and in this manner parallel recalibrate operations may be done on up to four drives at once. upon power up, the software must issue a recalibrate command to properly initialize all drives and the controller. seek the read/write head within the drive is moved from track to track under the control of the seek command. the fdc compares the pcn, which is the current head position, with the ncn and performs the following operation if there is a difference: pcn < ncn: direction signal to drive set to "1" (step in) and issues step pulses. pcn > ncn: direction signal to drive set to "0" (step out) and issues step pulses. the rate at which step pulses are issued is controlled by srt (stepping rate time) in the specify command. after each step pulse is issued, ncn is compared against pcn, and when ncn = pcn the se bit in status register 0 is set to "1" and the command is terminated. during the command phase of the seek or recalibrate operation, the fdc is in the busy state, but during the execution phase it is in the non-busy state. at this time, another seek or recalibrate command may be issued, and in this manner, parallel seek operations may be done on up to four drives at once. note that if implied seek is not enabled, the read and write commands should be preceded by: seek command - step to the proper track sense interrupt status command - terminate the seek command read id - verify head is on proper track issue read/write command. the seek command does not have a result phase. therefore, it is highly recommended that the sense interrupt status command be issued after the seek command to terminate it and to provide verification of the head position (pcn). the h bit (head address) in st0 will always return to a "0". when exiting powerdown mode, the fdc clears the pcn value and the status information to zero. prior to issuing the powerdown command, it is highly recommended that the user service all pending interrupts through the sense interrupt status command.
73 sense interrupt status an interrupt signal on the fdc?s irq pin is generated by the fdc for one of the following reasons: upon entering the result phase of: read data command read a track command read id command read deleted data command write data command format a track command write deleted data command verify command end of seek, relative seek, or recalibrate command fdc requires a data transfer during the execution phase in the non-dma mode the sense interrupt status command resets the interrupt signal and, via the ic code and se bit of status register 0, identifies the cause of the interrupt. table 43 - interrupt identification se ic interrupt due to 0 1 1 11 00 01 polling normal termination of seek or recalibrate command abnormal termination of seek or recalibrate command the seek, relative seek, and recalibrate commands have no result phase. the sense interrupt status command must be issued immediately after these commands to terminate them and to provide verification of the head position (pcn). the h (head address) bit in st0 will always return a "0". if a sense interrupt status is not issued, the drive will continue to be busy and may affect the operation of the next command. sense drive status sense drive status obtains drive status information. it has no execution phase and goes directly to the result phase from the command phase. status register 3 contains the drive status information. specify the specify command sets the initial values for each of the three internal times. the hut (head unload time) defines the time from the end of the execution phase of one of the read/write commands to the head unload state. the srt (step rate time) defines the time interval between adjacent step pulses. note that the spacing between the first and second step pulses may be shorter than the remaining step pulses. the hlt (head load time) defines the time between when the head load signal goes high and the read/write operation starts. the values change with the data rate speed selection and are documented in table 44 - drive control delays (ms). the values are the same for mfm and fm.
74 table 44 - drive control delays(ms) hut srt 2m 1m 500k 300k 250k 2m 1m 500k 300k 250k 0 1 .. e f 64 4 .. 56 60 128 8 .. 112 120 256 16 .. 224 240 426 26.7 .. 373 400 512 32 .. 448 480 4 3.75 .. 0.5 0.25 8 7.5 .. 1 0.5 16 15 .. 2 1 26.7 25 .. 3.33 1.67 32 30 .. 4 2 hlt 2m 1m 500k 300k 250k 00 01 02 .. 7f 7f 64 0.5 1 .. 63 63.5 128 1 2 .. 126 127 256 2 4 .. 252 254 426 3.3 6.7 .. 420 423 512 4 8 . 504 508 the choice of dma or non-dma operations is made by the nd bit. when this bit is "1", the non-dma mode is selected, and when nd is "0", the dma mode is selected. in dma mode, data transfers are signalled by the fdc?s drq pin. non-dma mode uses the rqm bit and the fdc?s irq pin to signal data transfers. configure the configure command is issued to select the special features of the fdc. a configure command need not be issued if the default values of the fdc meet the system requirements. configure default values: eis - no implied seeks efifo - fifo disabled poll - polling enabled fifothr - fifo threshold set to 1 byte pretrk - pre-compensation set to track 0 eis - enable implied seek. when set to "1", the fdc will perform a seek operation before executing a read or write command. defaults to no implied seek. efifo - a "1" disables the fifo (default). this means data transfers are asked for on a byte- by-byte basis. defaults to "1", fifo disabled. the threshold defaults to "1". poll - disable polling of the drives. defaults to "0", polling enabled. when enabled, a single interrupt is generated after a reset. no polling is performed while the drive head is loaded and the head unload delay has not expired. fifothr - the fifo threshold in the execution phase of read or write commands. this is programmable from 1 to 16 bytes. defaults to one byte. a "00" selects one byte; "0f" selects 16 bytes. pretrk - pre-compensation start track number. programmable from track 0 to 255. defaults to track 0. a "00" selects track 0; "ff" selects track 255.
75 version the version command checks to see if the controller is an enhanced type or the older type (765a). a value of 90 h is returned as the result byte. relative seek the command is coded the same as for seek, except for the msb of the first byte and the dir bit. dir action 0 1 step head out step head in dir head step direction con trol rcn relative cylinder number that determines how many tracks to step the head in or out from the current track number. the relative seek command differs from the seek command in that it steps the head the absolute number of tracks specified in the command instead of making a comparison against an internal register. the seek command is good for drives that support a maximum of 256 tracks. relative seeks cannot be overlapped with other relative seeks. only one relative seek can be active at a time. relative seeks may be overlapped with seeks and recalibrates. bit 4 of status register 0 (ec) will be set if relative seek attempts to step outward beyond track 0. as an example, assume that a floppy drive has 300 useable tracks. the host needs to read track 300 and the head is on any track (0-255). if a seek command is issued, the head will stop at track 255. if a relative seek command is issued, the fdc will move the head the specified number of tracks, regardless of the internal cylinder position register (but will increment the register). if the head was on track 40 (d), the maximum track that the fdc could position the head on using relative seek will be 295 (d), the initial track + 255 (d). the maximum count that the head can be moved with a single relative seek command is 255 (d). the internal register, pcn, will overflow as the cylinder number crosses track 255 and will contain 39 (d). the resulting pcn value is thus (rcn + pcn) mod 256. functionally, the fdc starts counting from 0 again as the track number goes above 255 (d). it is the user's responsibility to compensate fdc functions (precompensation track number) when accessing tracks greater than 255. the fdc does not keep track that it is working in an "extended track area" (greater than 255). any command issued will use the current pcn value except for the recalibrate command, which only looks for the track0 signal. recalibrate will return an error if the head is farther than 79 due to its limitation of issuing a maximum of 80 step pulses. the user simply needs to issue a second recalibrate command. the seek command and implied seeks will function correctly within the 44 (d) track (299-255) area of the "extended track area". it is the user's responsibility not to issue a new track position that will exceed the maximum track that is present in the extended area. to return to the standard floppy range (0-255) of tracks, a relative seek should be issued to cross the track 255 boundary. a relative seek can be used instead of the normal seek, but the host is required to calculate the difference between the current head location and the new (target) head location. this may require the host to issue a read id command to ensure that the head is physically on the track that software assumes it to be. different fdc commands will return different cylinder results which may be difficult to keep track of with software without the read id command.
76 perpendicular mode the perpendicular mode command should be issued prior to executing read/write/format commands that access a disk drive with perpendicular recording capability. with this command, the length of the gap2 field and vco enable timing can be altered to accommodate the unique requirements of these drives. table 54 describes the effects of the wgate and gap bits for the perpendicular mode command. upon a reset, the fdc will default to the conventional mode (wgate = 0, gap = 0). selection of the 500 kbps and 1 mbps perpendicular modes is independent of the actual data rate selected in the data rate select register. the user must ensure that these two data rates remain consistent. the gap2 and vco timing requirements for perpendicular recording type drives are dictated by the design of the read/write head. in the design of this head, a pre-erase head precedes the normal read/write head by a distance of 200 micrometers. this works out to about 38 bytes at a 1 mbps recording density. whenever the write head is enabled by the write gate signal, the pre-erase head is also activated at the same time. thus, when the write head is initially turned on, flux transitions recorded on the media for the first 38 bytes will not be preconditioned with the pre-erase head since it has not yet been activated. to accommodate this head activation and deactivation time, the gap2 field is expanded to a length of 41 bytes. the format field illustrates the change in the gap2 field size for the perpendicular format. on the read back by the fdc, the controller must begin synchronization at the beginning of the sync field. for the conventional mode, the internal pll vco is enabled (vcoen) approximately 24 bytes from the start of the gap2 field. but, when the controller operates in the 1 mbps perpendicular mode (wgate = 1, gap = 1), vcoen goes active after 43 bytes to accommodate the increased gap2 field size. for both cases, and approximate two-byte cushion is maintained from the beginning of the sync field for the purposes of avoiding write splices in the presence of motor speed variation. for the write data case, the fdc activates write gate at the beginning of the sync field under the conventional mode. the controller then writes a new sync field, data address mark, data field, and crc. with the pre-erase head of the perpendicular drive, the write head must be activated in the gap2 field to insure a proper write of the new sync field. for the 1 mbps perpendicular mode (wgate = 1, gap = 1), 38 bytes will be written in the gap2 space. since the bit density is proportional to the data rate, 19 bytes will be written in the gap2 field for the 500 kbps perpendicular mode (wgate = 1, gap =0). it should be noted that none of the alterations in gap2 size, vco timing, or write gate timing affect normal program flow. the information provided here is just for background purposes and is not needed for normal operation. once the perpendicular mode command is invoked, fdc software behavior from the user standpoint is unchanged. the perpendicular mode command is enhanced to allow specific drives to be designated perpendicular recording drives. this enhancement allows data transfers between conventional and perpendicular drives without having to issue perpendicular mode commands between the accesses of the different drive types, nor having to change write pre- compensation values. when both gap and wgate bits of the perpendicular mode command are both programmed to "0" (conventional mode), then d0, d1, d2, d3, and d4 can be programmed independently to "1" for that drive to be set automatically to perpendicular mode. in this mode the following set of conditions also apply:
77 1. the gap2 written to a perpendicular drive during a write operation will depend upon the programmed data rate. 2. the write pre-compensation given to a perpendicular mode drive will be 0ns. 3. for d0-d3 programmed to "0" for conventional mode drives any data written will be at the currently programmed write pre-compensation. note: bits d0-d3 can only be overwritten when ow is programmed as a "1". if either gap or wgate is a "1" then d0-d3 are ignored. software and hardware resets have the following effect on the perpendicular mode command: 1. "software" resets (via the dor or dsr registers) will only clear gap and wgate bits to "0". d0-d3 are unaffected and retain their previous value. 2. "hardware" resets will clear all bits (gap, wgate and d0-d3) to "0", i.e all conventional mode. table 45 - effects of wgate and gap bits wgate gap mode length of gap2 format field portion of gap 2 written by write data operation 0 0 1 1 0 1 0 1 conventional perpendicular (500 kbps) reserved (conventional) perpendicular (1 mbps) 22 bytes 22 bytes 22 bytes 41 bytes 0 bytes 19 bytes 0 bytes 38 bytes
78 lock in order to protect systems with long dma latencies against older application software that can disable the fifo the lock command has been added. this command should only be used by the fdc routines, and application software should refrain from using it. if an application calls for the fifo to be disabled then the configure command should be used. the lock command defines whether the efifo, fifothr, and pretrk parameters of the configure command can be reset by the dor and dsr registers. when the lock bit is set to logic "1" all subsequent "software resets by the dor and dsr registers will not change the previously set parameters to their default values. all "hardware" reset from the reset pin will set the lock bit to logic "0" and return the efifo, fifothr, and pretrk to their default values. a status byte is returned immediately after issuing a a lock command. this byte reflects the value of the lock bit set by the command byte. enhanced dumpreg the dumpreg command is designed to support system run-time diagnostics and application software development and debug. to accommodate the lock command and the enhanced perpendicular mode command the eighth byte of the dumpreg command contains the data from these two commands. compatibility the FDC37N972 was designed with software compatibility in mind. it is a fully backwards- compatible solution with the older generation 765a/b disk controllers. the fdc also implements on-board registers for compatibility with the ps/2, as well as pc/at and pc/xt, fdc subsystems. after a hardware reset of the fdc, all registers, functions and enhancements default to a pc/at, ps/2 or ps/2 model 30 compatible operating mode, depending on how the ident and mfm bits are configured by the system bios. parallel port fdc refer to the parallel port section for details. hot swappable fdd capability the fdc output pins will tri-state whenever the fdc logical device is powered-down or not activated. in addition setting bit 7 of the fdd mode configuration register (ld0_crf0) will tri- state the fdc output pins. bit 7 only affects the standard fdc interface, it has no effect on the parallel port floppy interface. the following table illustrates the state of the fdc and parallel port fdc pins for combinations of 1) the fdc output control bit; 2) the activate bit; and 3) the fdc powerdown state. table - 46 fdc hot swapping state of the fdc and parallel port fdc pins fdd mode register, bit[7] activate bit fdc in power down fdc pins parallel port fdc pins x 0 x hi-z hi-z x 1 y hi-z hi-z 0 1 n active active 1 1 n hi-z active
79 when the fdc is disabled, powered down or inactive the fdc output pins will tri-state allowing ?hot- swapping? of the floppy disk drive. the following table lists the five control/configuration mechanisms that power down or deactivate the fdc logical device. table 47 - fdc hot swapping mechanisms mechanism fdc output pins state tri- state tri-state tri-state tri-state (note 1) tri-state (note 2) fdc logical dev activate bit =0: fdc ld deactivated =1: fdc ld activated refer to the description of the fdc logical device configuration register 0x30 in the configuration section of the FDC37N972 specification. 0 x 1 1 1 fdc logical dev base address 0x100 < base < 0x0ff8: fdc ld base address valid. 0xfff < base < 0x100: fdc ld base address invalid. refer to the description of the fdc base i/o address registers in the configuration section of the FDC37N972 specification. x invalid base address valid base address valid base address valid base address gcr 0x22 bit-0 (fdc power) =0: power off =1: power on refer to the description of the global config register 0x22 in the configuration section of the FDC37N972 specification. x x 0 1 1 dsr, bit-6 (pwr down) =0: normal run =1: manual pwr down refer to the description of the dsr in the fdc section of any smsc super or ultra i/o data sheet. x x x 1 0
80 mechanism fdc output pins state gcr 0x23 bit-0 (fdc auto power management) =1: pwr mngnt on =0: pwr mngnt off refer to the description of the global config register 0x23 in the configuration section of the FDC37N972 specification. x x x x 1 note: fdc output pins = nwdata, drvden0, nhdselm nwgate, ndir, nstep, nds1, nds0, nmtr0, nmtr1. note1: dsr pwr down overrides auto pwr down. note 2: outputs tri-state only if all of the required auto power down conditio ns are met, otherwise outputs are active. see auto power management section of the fdc37c93x data sheet.
81 fdc force write protect the FDC37N972 includes a force write protect function for the floppy disk controller. force write protect asserts the internal nwrtprt input to the controller ( table 48 and figure 6 ). nwrtprt fdc nds0 nds1 nwrtprt nds0 nds1 force wrtprt figure 6 - force write protect function note: this figure is for illustration purposes only and is not intended to suggest specific implementation details. the force wrtprt bit is d0 in the disable register (see section disable register on page 166). the force wrtprt bit is active- high and set to ?0? by default. the force write protect function applies to the nwrtprt input from the fdd interface as well as the nwrtprt input from the parallel port fdc. table 48 - force wrtprt function nwrtprt (fdd pin) force wrtprt nds0 nds1 nwrtprt (fdc) description 0 x x x 0 active nwrtprt pin function is always enabled. 1 1 1 1 1 1 0 1 1 1 nwrtprt function inactive. 1 1 0 1 0 1 1 1 0 0 enabled force wrtprt function overrides an inactive nwrtprt pin.
82 acpi embedded controller overview acpi defines a standard hardware and software communications interface between the os and an embedded controller. this interface allows the os to support a standard driver that can directly communicate with the embedded controller, allowing other drivers within the system to communicate with and use the ec resources; for example, smart battery and aml code. the FDC37N972 contains an embedded controller interface (eci) to handle sci wake and run-time event processing ( figure 8 ). the eci is configured in logical device number 8 in the FDC37N972 configuration register map and presents an 8042-style interface to the isa host. ec (arbitrates wake and run-time sci events) chipset gpex gpey run-time wake (wake) ring (run-time) thermal (run-time) dock (wake & run-time) battery figure 7 ? embedded control (ec) illustration ec input buffer ec output buffer ec status register sci interface code main firmware (8051) i/o acpi interface run-time wake sci interface command write data write data read status read figure 8 ? generic acpi ec block diagram
83 eci configuration registers the three device configuration registers in ldn8 provide eci activation control and the base address for the eci run-time registers (table 49 ). register 0x30 is the activate register. the activate register qualifies address decoding for the eci; e.g., if the activate bit d0 in the activate register is ?0?, eci addresses will not be decoded; if the activate bit is ?1?, eci addresses will be decoded depending on the values programmed in the eci primary base address registers. registers 0x60 and 0x61 are the eci primary base address registers. register 0x60 is the eci primary base address high byte, register 0x61 is the eci primary base address low byte. note: bits d0 and d2 in the eci primary base address low byte must be ?0?. for example, 0x62 is a valid eci base address, while 0x66 is not a valid eci base address. the valid eci primary base address range is 0x0000 ? 0x0ffa. table 49 - eci configuration registers (ldn8) index type hard reset soft reset vcc2 por vcc1& vcc0 por description d7 d6 d5 d4 d3 d2 d1 d0 0x30 r/w 0x00 0x00 0x00 - activate reserved activate 0x60 r/w 0x00 0x00 0x00 - eci primary base address high byte 0x61 r/w 0x62 0x62 0x62 - eci primary base address low byte 1 a7 a6 a5 a4 a3 ?0? a1 ?0? note 1 bits d0 and d2 of the eci base address low byte must be ?0?. eci runtime registers an acpi-compliant eci contains three registers: ec_command, ec_status, and ec_data. the eci registers occupy two addresses in the host i/o space (table 50 ). the ec_data and ec_command registers appear as a single 8-bit data register in the 8051. the cmd bit in the ec_status register is used by the 8051 to discriminate commands from data written by the host to the eci. cmd is controlled by hardware: host writes to the ec_data register set cmd = ?0?; host writes to the ec_command register set cmd = ?1?. descriptions of these registers follow in the sections below.
84 table 50 - eci run-time registers isa host interface 8051 interface register name host index host type cmd 1 8051 index (7f00+) 8051 type power plane vcc1 por vcc2 por ec_data eci base address r/w 0 0x53 r/w vcc1 - - ec_command eci base address + 4 w 1 0x53 r vcc1 - - ec_status eci base address + 4 r - 0x54 r/w vcc1 0x00 - note 1 cmd is bit d3 in the ec_status register. ec_status register the ec_status register indicates the state of the embedded controller interface. to the host, the ec_status register is read-only. to the 8051, some bits in the ec_status register are read-only (table 51 ). these bits are controlled by hardware. the 8051 software controlled bits in the ec_status register are read/write. table 51 ? ec_status register d7 d6 d5 d4 d3 d2 d1 d0 host type r r r r r r r r 8051 type r/w r/w r/w r/w r r/w r r name ud 1 smi_evt sci_evt burst cmd ud 1 ibf obf note 1 the ud bits are user-defined. ud bits are maintained by 8051 software, only. obf bit ? d0 the output buffer full (obf) flag is set when the 8051 writes a byte of data into the data port (ec_data), but the host has not yet read it. once the host reads the status byte and sees the obf flag set, the host reads the data port to get the byte of data that the 8051 has written. once the host reads the data, the obf flag is automatically cleared by hardware. an ec_obf interrupt signals the 8051 that the data has been read by the host and the 8051 is free to write more data to the ec_data register. the ec_obf interrupt is generated whenever the obf bit in the ec_status register is reset. the ec_obf interrupt is routed to bit 3 in the int0 src register (figure 19 ). the ec_obf interrupt mask is bit 4 in the int1 mask register. ibf bit ? d1 the input buffer full (ibf) flag is set when the host has written a byte of data to the command or data port, but the 8051 has not yet read it. an ec_ibf interrupt signals the 8051 that there is data available. once the 8051 reads the status byte and sees the ibf flag set, the 8051 reads the data port to get the byte of data that the host has written. once the 8051 reads the data, the ibf flag is automatically cleared by hardware. the 8051 must then generate a software interrupt (sci) to
85 alert the host that the data has been read and that the host is free to write more data to the eci as needed. an ec_ibf interrupt is generated whenever the ibf bit in the ec_status register is set. the ec_ibf interrupt is routed to bit 4 in the int0 src register. the ec_ibf interrupt mask is bit 5 in the int1 mask register. cmd bit ? d3 the cmd bit is ?1? when the ec_data register contains a command byte; the cmd bit is ?0? when the ec_data register contains a data byte. the cmd bit is controlled by hardware: host writes to the ec_data register set cmd = ?0?; host writes to the ec_command register set cmd = ?1?. the cmd bit allows the embedded controller to differentiate the start of a command sequence from a data byte write operation. burst bit ? d4 the burst bit is ?1? when the ec is in burst mode for polled command processing; the burst bit is ?0? when the ec is in normal mode for interrupt-driven command processing. the burst bit is an 8051-maintained software flag that indicates the embedded controller has received the burst enable command from the host, has halted normal processing, and is waiting for a series of commands to be sent from the host. burst mode allows the os or system management handler to quickly read and write several bytes of data at a time without the overhead of scis between commands. sci_evt bit ? d5 the sci event flag sci_evt is ?1? when an sci event is pending; i.e., the 8051 is requesting an sci query; sci_evt is ?0? when no sci events are pending. the sci_evt bit is an 8051-maintained software flag that is set when the embedded controller has detected an internal event that requires operating system attention. the ec sets sci_evt before generating an sci to the os. smi_evt bit ? d6 the smi event flag smi_evt is ?1? when an smi event is pending; i.e., the 8051 is requesting an smi query; smi_evt is ?0? when no smi events are pending. the smi_evt bit is an 8051-maintained software flag that is set when the embedded controller has detected an internal event that requires system management interrupt handler attention. the ec sets smi_evt before generating an smi. ec_command register the ec_command register is a write-only register that allows the host to issue commands to the embedded controller. writes to the ec_command register are latched in the 8051 data register and the input buffer full flag is set in the ec_status register. writes to the ec_command register also cause the cmd bit to be set to ?1? in the ec_status register. ec_data register the ec_data register is a read/write register that allows the host to issue command arguments to the embedded controller and allows the os to read data returned by the embedded controller. host writes to the ec_data register are latched in the 8051 data register and the input buffer full flag is set in the ec_status register. host writes to the ec_data register also cause the
86 cmd bit to be reset to ?0? in the ec_status register. host reads from the ec_data register return data from the 8051 data register and clear the output buffer full flag in the ec_status register. serial port (uart) the FDC37N972 incorporates one full function uart. the uart is compatible with the ns16450, the 16450 ace registers and the nsc16550a. the uart performs serial-to- parallel conversion on received characters and parallel-to-serial conversion on transmit characters. the data rates are independently programmable from 460.8k baud down to 50 baud. the character options are programmable for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky or no parity; and prioritized interrupts. the uart contains a programmable baud rate generator that is capable of dividing the input clock or crystal by a number from 1 to 65535. the uart is also capable of supporting the midi data rate. refer to the configuration registers for information on disabling, power down and changing the base address of the uart. the interrupt from a uart is enabled by programming out2 of the uart to a logic "1". out2 being a logic "0" disables that uart's interrupt. register description addressing of the accessible registers of the serial port is shown below. the base addresses of the serial ports are defined by the configuration registers (see configuration section). the serial port registers are located at sequentially increasing addresses above these base addresses. the FDC37N972 contains a serial port, which contains a register set as described below.
87 table 52 - addressing the serial port dlab* a2 a1 a0 register name 0 0 0 0 receive buffer (read) 0 0 0 0 transmit buffer (write) 0 0 0 1 interrupt enable (read/write) x 0 1 0 interrupt identification (read) x 0 1 0 fifo control (write) x 0 1 1 line control (read/write) x 1 0 0 modem control (read/write) x 1 0 1 line status (read/write) x 1 1 0 modem status (read/write) x 1 1 1 scratchpad (read/write) 1 0 0 0 divisor lsb (read/write) 1 0 0 1 divisor msb (read/write) note: dlab is bit 7 of the line control register the following section describes the operation of the registers. receive buffer register (rb) address offset = 0h, dlab = 0, read only this register holds the received incoming data byte. bit 0 is the least significant bit, which is transmitted and received first. received data is double buffered; this uses an additional shift register to receive the serial data stream and convert it to a parallel 8 bit word which is transferred to the receive buffer register. the shift register is not accessible. transmit buffer register (tb) address offset = 0h, dlab = 0, write only this register contains the data byte to be transmitted. the transmit buffer is double buffered, utilizing an additional shift register (not accessible) to convert the 8 bit data word to a serial format. this shift register is loaded from the transmit buffer when the transmission of the previous byte is complete. interrupt enable register (ier) address offset = 1h, dlab = 0, read/write the lower four bits of this register control the enables of the five interrupt sources of the serial port interrupt. it is possible to totally disable the interrupt system by resetting bits 0 through 3 of this register. similarly, setting the appropriate bits of this register to a high, selected interrupts can be enabled. disabling the interrupt system inhibits the interrupt identification register and disables any serial port interrupt out of the FDC37N972 . all other system functions operate in their normal manner, including the line status and modem status registers. the contents of the interrupt enable register are described below.
88 bit 0 this bit enables the received data available interrupt (and timeout interrupts in the fifo mode) when set to logic "1". bit 1 this bit enables the transmitter holding register empty interrupt when set to logic "1". bit 2 this bit enables the received line status interrupt when set to logic "1". the error sources causing the interrupt are overrun, parity, framing and break. the line status register must be read to determine the source. bit 3 this bit enables the modem status interrupt when set to logic "1". this is caused when one of the modem status register bits changes state. bits 4 - 7 these bits are always logic "0". fifo control register (fcr) address offset = 2h, dlab = x, write this is a write only register at the same location as the iir. this register is used to enable and clear the fifos, set the rcvr fifo trigger level. note: dma is not supported. bit 0 setting this bit to a logic "1" enables both the xmit and rcvr fifos. clearing this bit to a logic "0" disables both the xmit and rcvr fifos and clears all bytes from both fifos. when changing from fifo mode to non-fifo (16450) mode, data is automatically cleared from the fifos. this bit must be a 1 when other bits in this register are written to or they will not be properly programmed. bit 1 setting this bit to a logic "1" clears all bytes in the rcvr fifo and resets its counter logic to ?0?. the shift register is not cleared. this bit is self-clearing. bit 2 setting this bit to a logic "1" clears all bytes in the xmit fifo and resets its counter logic to ?0?. the shift register is not cleared. this bit is self-clearing. bit 3 writing to this bit has no effect on the operation of the uart. the rxrdy and txrdy pins are not available on this chip.
89 bits 4 and 5 reserved bits 6 and 7 these bits are used to set the trigger level for the rcvr fifo interrupt. bit 7 bit 6 rcvr fifo trigger level (bytes) 0 0 1 0 1 4 1 0 8 1 1 14 interrupt identification register (iir) address offset = 2h, dlab = x, read by accessing this register, the host cpu can determine the highest priority interrupt and its source. four levels of priority interrupt exist. they are in descending order of priority: 1. receiver line status (highest priority) 2. received data ready 3. transmitter holding register empty 4. modem status (lowest priority) information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the interrupt identification register (refer to interrupt control table). when the cpu accesses the iir, the serial port freezes all interrupts and indicates the highest priority pending interrupt to the cpu. during this cpu access, even if the serial port records new interrupts, the current indication does not change until access is completed. the contents of the iir are described below. bit 0 this bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending. when bit 0 is a logic "0", an interrupt is pending and the contents of the iir may be used as a pointer to the appropriate internal service routine. when bit 0 is a logic "1", no interrupt is pending. bits 1 and 2 these two bits of the iir are used to identify the highest priority interrupt pending as indicated by the interrupt control table. bit 3 in non-fifo mode, this bit is a logic "0". in fifo mode this bit is set along with bit 2 when a timeout interrupt is pending.
90 bits 4 and 5 these bits of the iir are always logic "0". bits 6 and 7 these two bits are set when the fifo control register bit 0 equals 1. table 53 - interrupt control table fifo mode only interrupt identification register interrupt set and reset functions bit 3 bit 2 bit 1 bit 0 priority level interrupt type interrupt source interrupt reset control 0 0 0 1 - none none - 0 1 1 0 highest receiver line status overrun error, parity error, framing error or break interrupt reading the line status register 0 1 0 0 second received data available receiver data available read receiver buffer or the fifo drops below the trigger level. 1 1 0 0 second character timeout indication no characters have been removed from or input to the rcvr fifo during the last 4 char times and there is at least 1 char in it during this time reading the receiver buffer register 0 0 1 0 third transmitter holding register empty transmitter holding register empty reading the iir register (if source of interrupt) or writing the transmitter holding register 0 0 0 0 fourth modem status clear to send or data set ready or ring indicator or data carrier detect reading the modem status register
91 line control register (lcr) address offset = 3h, dlab = 0, read/write this register contains the format information of the serial line. the bit definitions are: bits 0 and 1 these two bits specify the number of bits in each transmitted or received serial character. the encoding of bits 0 and 1 is as follows: bit 1 bit 0 word length 0 0 1 1 0 1 0 1 5 bits 6 bits 7 bits 8 bits the start, stop and parity bits are not included in the word length. bit 2 this bit specifies the number of stop bits in each transmitted or received serial character. the following table summarizes the information. bit 2 word length number of stop bits 0 -- 1 1 5 bits 1.5 1 6 bits 2 1 7 bits 2 1 8 bits 2 note: the receiver will ignore all stop bits beyond the first, regardless of the number used in transmitting. bit 3 parity enable bit. when bit 3 is a logic "1", a parity bit is generated (transmit data) or checked (receive data) between the last data word bit and the first stop bit of the serial data. (the parity bit is used to generate an even or odd number of 1s when the data word bits and the parity bit are summed). bit 4 even parity select bit. when bit 3 is a logic "1" and bit 4 is a logic "0", an odd number of logic "1"'s is transmitted or checked in the data word bits and the parity bit. when bit 3 is a logic "1" and bit 4 is a logic "1" an even number of bits is transmitted and checked. bit 5 stick parity bit. when bit 3 is a logic "1" and bit 5 is a logic "1", the parity bit is transmitted and then detected by the receiver in the opposite state indicated by bit 4.
92 bit 6 set break control bit. when bit 6 is a logic "1", the transmit data output (txd) is forced to the spacing or logic "0" state and remains there (until reset by a low level bit 6) regardless of other transmitter activity. this feature enables the serial port to alert a terminal in a communications system. bit 7 divisor latch access bit (dlab). it must be set high (logic "1") to access the divisor latches of the baud rate generator during read or write operations. it must be set low (logic "0") to access the receiver buffer register, the transmitter holding register, or the interrupt enable register. modem control register (mcr) address offset = 4h, dlab = x, read/write this 8 bit register controls the interface with the modem or data set (or device emulating a modem). the contents of the modem control register are described below. bit 0 this bit controls the data terminal ready (ndtr) output. when bit 0 is set to a logic "1", the ndtr output is forced to a logic "0". when bit 0 is a logic "0", the ndtr output is forced to a logic "1". bit 1 this bit controls the request to send (nrts) output. bit 1 affects the nrts output in a manner identical to that described above for bit 0. bit 2 this bit controls the output 1 (out1) bit. this bit does not have an output pin and can only be read or written by the cpu. bit 3 output 2 (out2). this bit is used to enable an uart interrupt. when out2 is a logic "0", the serial port interrupt output is forced to a high impedance state - disabled. when out2 is a logic "1", the serial port interrupt outputs are enabled. bit 4 this bit provides the loopback feature for diagnostic testing of the serial port. when bit 4 is set to logic "1", the following occur: 1. the txd is set to the marking state(logic "1"). 2. the receiver serial input (rxd) is disconnected. 3. the output of the transmitter shift register is "looped back" into the receiver shift register input. 4. all modem control inputs (ncts, ndsr, nri and ndcd) are disconnected. 5. the four modem control outputs (ndtr, nrts, out1 and out2) are internally connected to the four modem control inputs (ndsr, ncts, ri, dcd). 6. the modem control output pins are forced inactive high. 7. data that is transmitted is immediately received.
93 this feature allows the processor to verify the transmit and receive data paths of the serial port. in the diagnostic mode, the receiver and the transmitter interrupts are fully operational. the modem control interrupts are also operational but the interrupts' sources are now the lower four bits of the modem control register instead of the modem control inputs. the interrupts are still controlled by the interrupt enable register. bits 5 - 7 these bits are permanently set to logic zero. line status register (lsr) address offset = 5h, dlab = x, read/write bit 0 data ready (dr). it is set to a logic "1" whenever a complete incoming character has been received and transferred into the receiver buffer register or the fifo. bit 0 is reset to a logic "0" by reading all of the data in the receive buffer register or the fifo. bit 1 overrun error (oe). bit 1 indicates that data in the receiver buffer register was not read before the next character was transferred into the register, thereby destroying the previous character. in fifo mode, an overrun error will occur only when the fifo is full and the next character has been completely received in the shift register, the character in the shift register is overwritten but not transferred to the fifo. the oe indicator is set to a logic "1" immediately upon detection of an overrun condition, and reset whenever the line status register is read. bit 2 parity error (pe). bit 2 indicates that the received data character does not have the correct even or odd parity, as selected by the even parity select bit. the pe is set to a logic "1" upon detection of a parity error and is reset to a logic "0" whenever the line status register is read. in the fifo mode this error is associated with the particular character in the fifo it applies to. this error is indicated when the associated character is at the top of the fifo. bit 3 framing error (fe). bit 3 indicates that the received character did not have a valid stop bit. bit 3 is set to a logic "1" whenever the stop bit following the last data bit or parity bit is detected as a zero bit (spacing level). the fe is reset to a logic "0" whenever the line status register is read. in the fifo mode this error is associated with the particular character in the fifo it applies to. this error is indicated when the associated character is at the top of the fifo. the serial port will try to resynchronize after a framing error. to do this, it assumes that the framing error was due to the next start bit, so it samples this 'start' bit twice and then takes in the 'data'. bit 4 break interrupt (bi). bit 4 is set to a logic "1" whenever the received data input is held in the spacing state (logic "0") for longer than a full word transmission time (that is, the total time of the start bit + data bits + parity bits + stop bits). the bi is reset after the cpu reads the contents of the line status
94 register. in the fifo mode this error is associated with the particular character in the fifo it applies to. this error is indicated when the associated character is at the top of the fifo. when break occurs only one zero character is loaded into the fifo. restarting after a break is received, requires the serial data (rxd) to be logic "1" for at least 1/2 bit time. note: bits 1 through 4 are the error conditions that produce a receiver line status interrupt whenever any of the corresponding conditions are detected and the interrupt is enabled. bit 5 transmitter holding register empty (thre). bit 5 indicates that the serial port is ready to accept a new character for transmission. in addition, this bit causes the serial port to issue an interrupt when the transmitter holding register interrupt enable is set high. the thre bit is set to a logic "1" when a character is transferred from the transmitter holding register into the transmitter shift register. the bit is reset to logic "0" whenever the cpu loads the transmitter holding register. in the fifo mode this bit is set when the xmit fifo is empty, it is cleared when at least 1 byte is written to the xmit fifo. bit 5 is a read only bit. bit 6 transmitter empty (temt). bit 6 is set to a logic "1" whenever the transmitter holding register (thr) and transmitter shift register (tsr) are both empty. it is reset to logic "0" whenever either the thr or tsr contains a data character. bit 6 is a read only bit. in the fifo mode this bit is set whenever the thr and tsr are both empty, bit 7 this bit is permanently set to logic "0" in the 450 mode. in the fifo mode, this bit is set to a logic "1" when there is at least one parity error, framing error or break indication in the fifo. this bit is cleared when the lsr is read if there are no subsequent errors in the fifo. modem status register (msr) address offset = 6h, dlab = x, read/write this 8 bit register provides the current state of the control lines from the modem (or peripheral device). in addition to this current state information, four bits of the modem status register (msr) provide change information. these bits are set to logic "1" whenever a control input from the modem changes state. they are reset to logic "0" whenever the modem status register is read. bit 0 delta clear to send (dcts). bit 0 indicates that the ncts input to the chip has changed state since the last time the msr was read. bit 1 delta data set ready (ddsr). bit 1 indicates that the ndsr input has changed state since the last time the msr was read.
95 bit 2 trailing edge of ring indicator (teri). bit 2 indicates that the nri input has changed from logic "0" to logic "1". bit 3 delta data carrier detect (ddcd). bit 3 indicates that the ndcd input to the chip has changed state. note: whenever bit 0, 1, 2, or 3 is set to a logic "1", a modem status interrupt is generated. bit 4 this bit is the complement of the clear to send (ncts) input. if bit 4 of the mcr is set to logic "1", this bit is equivalent to nrts in the mcr. bit 5 this bit is the complement of the data set ready (ndsr) input. if bit 4 of the mcr is set to logic "1", this bit is equivalent to dtr in the mcr. bit 6 this bit is the complement of the ring indicator (nri) input. if bit 4 of the mcr is set to logic "1", this bit is equivalent to out1 in the mcr. bit 7 this bit is the complement of the data carrier detect (ndcd) input. if bit 4 of the mcr is set to logic "1", this bit is equivalent to out2 in the mcr. scratchpad register (scr) address offset =7h, dlab =x, read/write this 8 bit read/write register has no effect on the operation of the serial port. it is intended as a scratchpad register to be used by the programmer to hold data temporarily.
96 programmable baud rate generator (and divisor latches dlh, dll) the serial port contains a programmable baud rate generator that is capable of taking any clock input (dc to 3 mhz) and dividing it by any divisor from 1 to 65535. this output frequency of the baud rate generator is 16x the baud rate. two 8 bit latches store the divisor in 16 bit binary format. these divisor latches must be loaded during initialization in order to insure desired operation of the baud rate generator. upon loading either of the divisor latches, a 16 bit baud counter is immediately loaded. this prevents long counts on initial load. if a 0 is loaded into the brg registers the output divides the clock by the number 3. if a 1 is loaded the output is the inverse of the input oscillator. if a two is loaded the output is a divide by 2 signal with a 50% duty cycle. if a 3 or greater is loaded the output is low for 2 bits and high for the remainder of the count. the input clock to the brg is the 24 mhz crystal divided by 13, giving a 1.8462 mhz clock. table 54 shows the baud rates possible with a 1.8462 mhz crystal. table 54 - uart baud rates desired baud rate divisor used to generate 16x clock percent error difference between desired and actual 1 high speed bit 2 50 2304 0.001 x 75 1536 - x 110 1047 - x 134.5 857 0.004 x 150 768 - x 300 384 - x 600 192 - x 1200 96 - x 1800 64 - x 2000 58 0.005 x 2400 48 - x 3600 32 - x 4800 24 - x 7200 16 - x 9600 12 - x 19200 6 - x 38400 3 0.030 x 57600 2 0.16 x 115200 1 0.16 x 230400 32770 0.16 1 460800 32769 0.16 1 note 1 : the percentage error for all baud rates, except where indicated otherwise, is 0.2%. note 2 : the high speed bit is located in the device configuration space. using 1.8462 mhz clock for <=38.4; using 1.843 mhz clock for 115.2k; using 3.6864 mhz clock for 230.4k; using 7.3728 mhz clock for 460.8k
97 fifo interrupt mode operation when the rcvr fifo and receiver interrupts are enabled (fcr bit 0 = "1", ier bit 0 = "1"), rcvr interrupts occur as follows: a. the receive data available interrupt will be issued when the fifo has reached its programmed trigger level; it is cleared as soon as the fifo drops below its programmed trigger level. b. the iir receive data available indication also occurs when the fifo trigger level is reached. it is cleared when the fifo drops below the trigger level. c. the receiver line status interrupt (iir=06h), has higher priority than the received data available (iir=04h) interrupt. d. the data ready bit (lsr bit 0) is set as soon as a character is transferred from the shift register to the rcvr fifo. it is reset when the fifo is empty. when rcvr fifo and receiver interrupts are enabled, rcvr fifo timeout interrupts occur as follows: a. a fifo timeout interrupt occurs if all the following conditions exist: - at least one character is in the fifo - the most recent serial character received was longer than 4 continuous character times ago. (if 2 stop bits are programmed, the second one is included in this time delay.) - the most recent cpu read of the fifo was longer than 4 continuous character times ago. this will cause a maximum character received to interrupt issued delay of 160 msec at 300 baud with a 12 bit character. b. character times are calculated by using the rclk input for a clock signal (this makes the delay proportional to the baudrate). c. when a timeout interrupt has occurred it is cleared and the timer reset when the cpu reads one character from the rcvr fifo. d. when a timeout interrupt has not occurred the timeout timer is reset after a new character is received or after the cpu reads the rcvr fifo. when the xmit fifo and transmitter interrupts are enabled (fcr bit 0 = "1", ier bit 1 = "1"), xmit interrupts occur as follows: a. the transmitter holding register interrupt (02h) occurs when the xmit fifo is empty; it is cleared as soon as the transmitter holding register is written to (1 of 16 characters may be written to the xmit fifo while servicing this interrupt) or the iir is read. b. the transmitter fifo empty indications will be delayed 1 character time minus the last stop bit time whenever the following occurs: thre=1 and there have not been at least two bytes at the same time in the transmitter fifo since the last thre=1. the transmitter interrupt after changing fcr0 will be immediate, if it is enabled. character timeout and rcvr fifo trigger level interrupts have the same priority as the current received data available interrupt; xmit fifo empty has the same priority as the current transmitter holding register empty interrupt. fifo polled mode operation with fcr bit 0 = "1" resetting ier bits 0, 1, 2 or 3 or all to zero puts the uart in the fifo polled mode of operation. since the rcvr and xmitter are controlled separately, either one or both can be in the polled mode of operation. in this mode, the user's program will check rcvr and xmitter status via the lsr. lsr definitions for the fifo polled mode are as follows: bit 0=1 as long as there is one byte in the rcvr fifo.
98 bits 1 to 4 specify which error(s) have occurred. character error status is handled the same way as when in the interrupt mode, the iir is not affected since eir bit 2=0. bit 5 indicates when the xmit fifo is empty. bit 6 indicates that both the xmit fifo and shift register are empty. bit 7 indicates whether there are any errors in the rcvr fifo. there is no trigger level reached or timeout condition indicated in the fifo polled mode, however, the rcvr and xmit fifos are still fully capable of holding characters. effect of the reset on register file the reset function table ( table 55 ) details the effect of v cc 2 por or nreset_out on each of the registers of the serial port. table 55 - reset function table register/signal reset control reset state interrupt enable register reset all bits low interrupt identification reg. reset bit 0 is high; bits 1 - 7 low fifo control reset all bits low line control reg. reset all bits low modem control reg. reset all bits low line status reg. reset all bits low except 5, 6 high modem status reg. reset bits 0 - 3 low; bits 4 - 7 input txd1, txd2 reset high intrpt (rcvr errs) reset/read lsr low intrpt (rcvr data ready) reset/read rbr low intrpt (thre) reset/readiir/write thr low out2b reset high rtsb reset high dtrb reset high out1b reset high rcvr fifo reset/ fcr1*fcr0/_fcr0 all bits low xmit fifo reset/ fcr1*fcr0/_fcr0 all bits low
99 table 56 - register summary for an individual uart channel register address* register name register symbol bit 0 bit 1 addr = 0 dlab = 0 receive buffer register (read only) rbr data bit 0 (note 1) data bit 1 addr = 0 dlab = 0 transmitter holding register (write only) thr data bit 0 data bit 1 addr = 1 dlab = 0 interrupt enable register ier enable received data available interrupt (erdai) enable transmitter holding register empty interrupt (ethrei) addr = 2 interrupt ident. register (read only) iir "0" if interrupt pending interrupt id bit addr = 2 fifo control register (write only) fcr fifo enable rcvr fifo reset addr = 3 line control register lcr word length select bit 0 (wls0) word length select bit 1 (wls1) addr = 4 modem control register mcr data terminal ready (dtr) request to send (rts) addr = 5 line status register lsr data ready (dr) overrun error (oe) addr = 6 modem status register msr delta clear to send (dcts) delta data set ready (ddsr) addr = 7 scratch register (note 4) scr bit 0 bit 1 addr = 0 dlab = 1 divisor latch (ls) ddl bit 0 bit 1 addr = 1 dlab = 1 divisor latch (ms) dlm bit 8 bit 9 *dlab is bit 7 of the line control register (addr = 3). note 1: bit 0 is the least significant bit. it is the first bit serially transmitted or received. note 2: when operating in the xt mode, this bit will be set any time that the transmitter shift register is empty.
100 table 56 - register summary for an individual uart channel (continued) bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 data bit 2 data bit 3 data bit 4 data bit 5 data bit 6 data bit 7 data bit 2 data bit 3 data bit 4 data bit 5 data bit 6 data bit 7 enable receiver line status interrupt (elsi) enable modem status interrupt (emsi) 0 0 0 0 interrupt id bit interrupt id bit (note 5) 0 0 fifos enabled (note 5) fifos enabled (note 5) xmit fifo reset dma mode select (note 6) reserved reserved rcvr trigger lsb rcvr trigger msb number of stop bits (stb) parity enable (pen) even parity select (eps) stick parity set break divisor latch access bit (dlab) out1 (note 3) out2 (note 3) loop 0 0 0 parity error (pe) framing error (fe) break interrupt (bi) transmitter holding register (thre) transmitter empty (temt) (note 2) error in rcvr fifo (note 5) trailing edge ring indicator (teri) delta data carrier detect (ddcd) clear to send (cts) data set ready (dsr) ring indicator (ri) data carrier detect (dcd) bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 note 3: this bit no longer has a pin associated with it. note 4: when operating in the xt mode, this register is not available. note 5: these bits are always zero in the non-fifo mode. note 6: writing a one to this bit has no effect. dma modes are not supported in this chip.
101 uart register summary notes: *dlab is bit 7 of the line control register (addr = 3). note 1: bit 0 is the least significant bit. it is the first bit serially transmitted or received. note 2: when operating in the xt mode, this bit will be set any time that the transmitter shift register is empty. note 3: this bit no longer has a pin associated with it. note 4: when operating in the xt mode, this register is not available. note 5: these bits are always zero in the non-fifo mode. note 6: writing a one to this bit has no effect. dma modes are not supported in this chip. notes on serial port fifo mode operation general the rcvr fifo will hold up to 16 bytes regardless of which trigger level is selected. tx and rx fifo operation the tx portion of the uart transmits data through txd as soon as the cpu loads a byte into the tx fifo. the uart will prevent loads to the tx fifo if it currently holds 16 characters. loading to the tx fifo will again be enabled as soon as the next character is transferred to the tx shift register. these capabilities account for the largely autonomous operation of the tx. the uart starts the above operations typically with a tx interrupt. the chip issues a tx interrupt whenever the tx fifo is empty and the tx interrupt is enabled, except in the following instance. assume that the tx fifo is empty and the cpu starts to load it. when the first byte enters the fifo the tx fifo empty interrupt will transition from active to inactive. depending on the execution speed of the service routine software, the uart may be able to transfer this byte from the fifo to the shift register before the cpu loads another byte. if this happens, the tx fifo will be empty again and typically the uart's interrupt line would transition to the active state. this could cause a system with an interrupt control unit to record a tx fifo empty condition, even though the cpu is currently servicing that interrupt. therefore, after the first byte has been loaded into the fifo the uart will wait one serial character transmission time before issuing a new tx fifo empty interrupt. this one character tx interrupt delay will remain active until at least two bytes have been loaded into the fifo, concurrently. when the tx fifo empties after this condition, the tx interrupt will be activated without a one character delay. rx support functions and operation are quite different from those described for the transmitter. the rx fifo receives data until the number of bytes in the fifo equals the selected interrupt trigger level. at that time if rx interrupts are enabled, the uart will issue an interrupt to the cpu. the rx fifo will continue to store bytes until it holds 16 of them. it will not accept any more data when it is full. any more data entering the rx shift register will set the overrun error flag. normally, the fifo depth and the programmable trigger levels will give the cpu ample time to empty the rx fifo before an overrun occurs.
102 one side-effect of having a rx fifo is that the selected interrupt trigger level may be above the data level in the fifo. this could occur when data at the end of the block contains fewer bytes than the trigger level. no interrupt would be issued to the cpu and the data would remain in the uart. to prevent the software from having to check for this situation the chip incorporates a timeout interrupt. the timeout interrupt is activated when there is a least one byte in the rx fifo, and neither the cpu nor the rx shift register has accessed the rx fifo within 4 character times of the last byte. the timeout interrupt is cleared or reset when the cpu reads the rx fifo or another character enters it. these fifo related features allow optimization of cpu/uart transactions and are especially useful given the higher baud rate capability (256 kbaud). infrared communications controller (ircc 2.0) the infrared communications controller is fully compliant to the irda specification version 1.1 which includes data rates up to 4 mbps to support irda-sira, irda-sirb, irda-hdlc and irda-fir modes. in addition the ircc 2.0 provides support for ask-ir, consumer (tv remote) ir, and raw-ir (host controller has direct access to the ir bit stream from/to the transceiver module). it is important to note that the ircc 2.0 block is a superset of a 16c550a uart. the ircc 2.0 includes an asynchronous communications engine (ace) and a separate synchronous communications engine (sce) to provide the full set of ir modes as well as the standard uart com mode. the ircc 2.0 block details are fully described in smsc?s specification titled ?infrared communications controller?. the information in this section of the specification will provide details on the integration of the fir logic block into the FDC37N972 . the infrared interface provides a two-way wireless communications port using infrared as a transmission medium. the ir transmission can use the standard irtx and irrx pins or optional irtx2 and irrx2 pins. these can be selected through the configuration registers. the irtx2 and irrx2 pins are alternate function pins. irda-sir allows serial communication at baud rates up to 115k baud. each word is sent serially beginning with a ?0? value start bit. a ?0? is signaled by sending a single ir pulse at the beginning of the serial bit time. a ?1? is signaled by sending no ir pulse during the bit time. please refer to the ac timing for the parameters of these pulses and the irda waveform. the amplitude shift keyed ir allows serial communication at baud rates up to 19.2k baud. each word is sent serially beginning with a ?0? value start bit. a ?0? is signaled by sending a 500 khz waveform for the duration of the serial bit time. a ?1? is signaled by sending no transmission the bit time. please refer to the ac timing for the parameters of the ask-ir waveform. if the half duplex option is chosen, there is a time-out when the direction of the transmission is changed. this time-out starts at the last bit transferred during a transmission and blocks the receiver input until the time-out expires. if the transmit buffer is loaded with more data before the time-out expires, the timer is restarted after the new byte is transmitted. if data is loaded into the transmit buffer while a character is being received, the transmission will not start until the time-out expires after the last receive bit has been received. if the start bit of another character is received during this time- out, the timer is restarted after the new character is received. the time-out is four character times. a character time is defined as 10 bit times regardless of the actual word length being used.
103 gpio9 gpio8 irtx irrx gpio6 gpio10 gpio6_out gpio10_out gpio8_out gpio9_out irtx2 irrx2 irtx irrx tx rx gpio9_in ircc 2.0 block raw tv ask irda fir com out mux com ir aux fast_bit g.p. data hp_mode fast misc7 1 misc[14:13] misc[16:15] frx_sel misc2 0 0 ir data reg bit-0 ir data reg bit-1 1 1 00 01 11 0 1 1 0 0 0 1 1 0 ?frx? ?ir_mode? figure 9 - integration of ircc 2.0 logic into the FDC37N972 hp_mode = (misc[14:13] == [1:0]) | (misc[16:15] == [1:0]) frx_sel = (misc[14:13] == [1:0]) overview 1. the FDC37N972 requires additional configuration register support to accommodate the ircc 2.0 core. 2. note: the ircc 2.0 is configured in logical device number 5. ld5 is still technically considered the serial port 2 block, even though uart2 is not included in the fdc37n97.
104 irrx/irtx pin enable when misc2=0 the irrx and irtx pins are enabled as when ircc 2.0 (ld5) is activated or enabled and the ircc 2.0 output mux is set to use the ir port, otherwise the irtx pin is tri-stated. when misc2=1, the irrx and irtx pins are always enabled as they can be bit banged through the ir data register, bits 1 and 0 respectively. therefore, if the ir interface is on irrx (pin 21) and irtx (pin 20), then misc2 allows the ir interface to be switched between the ircc 2.0 block and the ir data register. the ir data register is only available from the host, and is located at index register 98. this register is available through the mailbox register interface. ir registers - logical device 5 configuration registers overview in order to support the infrared communications controller ten configuration registers are included in logical device 5. refer to the configuration section of this specification for details. base i/o addresses 550 uart table 57 - asynchronous communications engine (uart) register register index base i/o range fixed register base offsets 0x60, 0x61 [0x100:0x0ff8] on 8 byte boundaries +0 : rb/tb ? lsb div +1 : ier ? msb div +2 : iir/fcr +3 : lcr +4 : mcr +5 : lsr +6 : msr +7 : scr register 0x60 stores the msb and 0x61 the lsb of the 550-uart?s 16 bit base address.
105 fast ir/sce table 58 - synchronous communications engine (sce) registers register index base i/o range fixed register base offsets 0x62, 0x63 [0x100:0x0ff8] on 8 byte boundaries +0 : register block, address 0 +1 : register block, address 1 +2 : register block, address 2 +3 : register block, address 3 +4 : register block, address 4 +5 : register block, address 5 +6 : register block, address 6 +7 : sce master control register register 0x60 stores the msb and 0x61 the lsb of the 550-uart?s 16 bit base address. note: refer to the infrared communications controller (ircc 2.0) specification for register details. note: if base i/o address is set below 0x100 then no decode will occur. ir dma channels dma channel 0, 1, 2 or 3 may be selected for use with the ircc 2.0 logic through the configuration registers of logical device 5. refer to the configuration section of this specification for further details on setting the dma channel and to the ircc 2.0 specification for details on ir dma transfers. ir irqs the interrupt (irq) for the ircc 2.0 logic is selectable through the configuration registers for logical device 5. refer to the configuration section of this specification for further details on setting the irq and to the ircc 2.0 specification for details on ir irq events. software select registers a and b the software select a and software select b registers in the FDC37N972 configuration space in logical device number 5 are directly connected to the read-only ircc 2.0 software select a & b registers in sce register block three. the FDC37N972 software select a register is ld5:crf7, the FDC37N972 software select b register is ld5:crf8. these registers are r/w. writing to ld5:crf7 is the only way to revise the contents of the software select a register in the ircc 2.0. writing the contents of the software select a register can only be done in the configuration state and only after the ldn has been set to ?5? and the csr has been initialized to ?f7h?. the default value of this register after power up is 00h ( table 59 ). writing to ld5:crf8 is the only way to revise the contents of the software select b register in the ircc 2.0. writing the contents of the software select b register can only be done in the configuration state and only after the ldn has been set to ?5? and the csr has been initialized to ?f8h?. the default value of this register after power up is 00h ( table 59 ).
106 table 59 - FDC37N972 software select a&b registers d7 d6 d5 d4 d3 d2 d1 d0 default ld5:crf7 r/w software select a 0x00 ld5:crf8 r/w software select b 0x00 ir half duplex timeout ld5:crf2 is the FDC37N972 ir half duplex time-out register ( table 60 ). in the FDC37N972, this register is linked to the ircc 2.0 ir half duplex time-out register. in the FDC37N972, these two registers must behave like the other ircc 2.0 legacy controls where either source uniformly updates the value of both registers registers when either register is explicitly written using iow or following a device-level por. ircc 2.0 software resets do not affect these registers. the ir half duplex time-out constrains the timing of transmit/receive direction mode changes in the ircc 2.0. the ir half duplex time-out is started as each ir message data bit is transferred and prevents direction mode changes until the time-out expires. the timer is restarted whenever new data is transferred in the current direction mode. the ir half duplex time-out is programmable from 0 to 25.5ms in 100 m s increments, as follows: ir half duplex time-out = (crf2) x 100 m m s table 60 - ir half duplex time-out register d7 d6 d5 d4 d3 d2 d1 d0 default ld5:crf2 r/w ir half duplex time-out 0x03 irtx output pins default the ircc 2.0 irtx pins default at power-up to ?output?, ?low? to prevent infrared transceiver damage. this default behavior applies to both the dedicated irtx2 pin and to gpio9 (see general purpose i/o (gpio) on page 265). parallel port the FDC37N972 incorporates an ibm xt/at compatible parallel port. this supports the optional ps/2 type bi-directional parallel port (spp), the enhanced parallel port (epp) and the extended capabilities port (ecp) parallel port modes. refer to the configuration registers for information on disabling, power down, changing the base address of the parallel port, and selecting the mode of operation. the parallel port also incorporates smsc's chiprotect circuitry, which prevents possible damage to the parallel port due to printer power- up. the functionality of the parallel port is achieved through the use of eight addressable ports, with their associated registers and control gating. the control and data port are read/write by the cpu, the status port is read/write in the epp mode. the address map of the parallel port is shown below:
107 table 61 - address map for parallel port register name address data port base address + 00h status port base address + 01h control port base address + 02h epp addr port base address + 03h epp data port 0 base address + 04h epp data port 1 base address + 05h epp data port 2 base address + 06h epp data port 3 base address + 07h table 62 - the bit map of these registers is: d0 d1 d2 d3 d4 d5 d6 d7 note data port pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 1 status port tmout 0 0 nerr slct pe nack nbusy 1 control port strobe alf ninit slc irqe pcd 0 0 1 epp addr port pd0 pd1 pd2 pd3 pd4 pd5 pd6 ad7 2,3 epp data port 0 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 2,3 epp data port 1 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 2,3 epp data port 2 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 2,3 epp data port 3 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 2,3 note 1: these registers are available in all modes. note 2: these registers are only available in epp mode. note 3 : for epp mode, iochrdy must be connected to the isa bus.
108 table 63 - parallel port connector pin map host connector pin number standard epp ecp 1 129 nstrobe nwrite nstrobe 2-9 124-121, 119-116 pdata<0:7> pdata<0:7> pdata<0:7> 10 115 nack intr nack 11 114 busy nwait busy, periphack(3) 12 113 pe (nu) perror, nackreverse(3) 13 112 select (nu) select 14 128 nalf ndatastb nalf, hostack(3) 15 127 nerror (nu) nfault(1) nperiphrequest(3) 16 126 ninit (nu) ninit(1) nreverserqst(3) 17 125 nselectin naddrstrb nselectin(1,3) (1)= compatible mode (3)= high speed mode note: for the cable interconnection required for ecp support and the slave connec tor pin numbers, refer to the ieee p1284 d2.0 standard, ?standard signaling method for a bi-directional parallel peripheral interface for personal computers? , september 10, 1993. this document is available from the ieee. ibm xt/at compatible, bi-directional and epp modes data port address offset = 00h the data port is located at an offset of '00h' from the base address. the data register is cleared at initialization by reset. during a write operation, the data register latches the contents of the data bus with the rising edge of the niow input. the contents of this register are buffered (non inverting) and output onto the pd0 -pd7 ports. during a read operation in spp mode, pd0 -pd7 ports are buffered (not latched) and output to the host cpu. status port address offset = 01h the status port is located at an offset of '01h' from the base address. the contents of this register are latched for the duration of an nior read cycle. the bits of the status port are defined as follows: bit 0 tmout - time out this bit is valid in epp mode only and indicates that a 10 m sec time out has occured on the epp bus. a logic ?0? means that no time out error has occured; a logic ?1? means that a time out error has been detected. this bit is cleared by a reset. writing a one to this bit clears the time out status bit. on a write, this bit is self clearing and does not require a write of a ?0?. writing a ?0? to this bit has no effect.
109 bits 1, 2 - are not implemented as register bits, during a read of the printer status register these bits are a low level. bit 3 nerr - nerror the level on the nerror input is read by the cpu as bit 3 of the printer status register. a logic 0 means an error has been detected; a logic ?1? means no error has been detected. bit 4 slct - printer selected status the level on the slct input is read by the cpu as bit 4 of the printer status register. a logic ?1? means the printer is on line; a logic 0 means it is not selected. bit 5 pe - paper end the level on the pe input is read by the cpu as bit 5 of the printer status register. a logic ?1? indicates a paper end; a logic 0 indicates the presence of paper. bit 6 nack - nacknowledge the level on the nack input is read by the cpu as bit 6 of the printer status register. a logic ?0? means that the printer has received a character and can now accept another. a logic ?1? means that it is still processing the last character or has not received the data. bit 7 nbusy - nbusy the complement of the level on the busy input is read by the cpu as bit 7 of the printer status register. a logic ?0? in this bit means that the printer is busy and cannot accept a new character. a logic ?1? means that it is ready to accept the next character. control port address offset = 02h the control port is located at an offset of '02h' from the base address. the control register is initialized by the reset input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low. bit 0 strobe - strobe this bit is inverted and output onto the nstrobe output. bit 1 alf - autofeed this bit is inverted and output onto the nalf output. a logic ?1? causes the printer to generate a line feed after each line is printed. a logic ?0? means no autofeed. bit 2 ninit - ninitiate output this bit is output onto the ninit output without inversion. bit 3 slctin - printer select input this bit is inverted and output onto the nslctin output. a logic ?1? on this bit selects the printer; a logic ?0? means the printer is not selected. bit 4 irqe - interrupt request enable the interrupt request enable bit when set to a high level may be used to enable interrupt requests from the parallel port to the cpu. an interrupt request is generated on the irq port by a positive going nack input. when the irqe bit is programmed low the irq is disabled. bit 5 pcd - parallel control direction parallel control direction is not valid in printer mode. in printer mode, the direction is always out regardless of the state of this bit. in bi- directional, epp or ecp mode, a logic 0 means that the printer port is in output mode (write); a logic ?1? means that the printer port is in input mode (read). bits 6 and 7 during a read are a low level, and cannot be written
110 epp address port address offset = 03h the epp address port is located at an offset of '03h' from the base address. the address register is cleared at initialization by reset. during a write operation, the contents of db0- db7 are buffered (non inverting) and output onto the pd0 - pd7 ports, the leading edge of n iow causes an epp address write cycle to be performed, the trailing edge of iow latches the data for the duration of the epp write cycle. during a read operation, pd0 -pd7 ports are read, the leading edge of ior causes an epp address read cycle to be performed and the data output to the host cpu, the deassertion of addrstb latches the pdata for the duration of the ior cycle. this register is only available in epp mode. epp data port 0 address offset = 04h the epp data port 0 is located at an offset of '04h' from the base address. the data register is cleared at initialization by reset. during a write operation, the contents of db0-db7 are buffered (non inverting) and output onto the pd0 -pd7 ports, the leading edge of niow causes an epp data write cycle to be performed, the trailing edge of iow latches the data for the duration of the epp write cycle. during a read operation, pd0 - pd7 ports are read, the leading edge of ior causes an epp read cycle to be performed and the data output to the host cpu, the deassertion of datastb latches the pdata for the duration of the ior cycle. this register is only available in epp mode. epp data port 1 address offset = 05h the epp data port 1 is located at an offset of '05h' from the base address. refer to epp data port 0 for a description of operation. this register is only available in epp mode. epp data port 2 address offset = 06h the epp data port 2 is located at an offset of '06h' from the base address. refer to epp data port 0 for a description of operation. this register is only available in epp mode. epp data port 3 address offset = 07h the epp data port 3 is located at an offset of '07h' from the base address. refer to epp data port 0 for a description of operation. this register is only available in epp mode. epp 1.9 operation when the epp mode is selected in the configuration register, the standard and bi- directional modes are also available. if no epp read, write or address cycle is currently executing, then the pdx bus is in the standard or bi-directional mode, and all output signals (strobe, alf, init) are as set by the spp control port and direction is controlled by pcd of the control port. in epp mode, the system timing is closely coupled to the epp timing. for this reason, a watchdog timer is required to prevent system lockup. the timer indicates if more than 10 m sec have elapsed from the start of the epp cycle (nior or niow asserted) to nwait being deasserted (after command). if a time-out occurs, the current epp cycle is aborted and the time-out condition is indicated in status bit 0.
111 during an epp cycle, if strobe is active, it overrides the epp write signal forcing the pdx bus to always be in a write mode and the nwrite signal to always be asserted. software constraints before an epp cycle is executed, the software must ensure that the control register bit pcd is a logic "0" (i.e. a 04h or 05h should be written to the control port). if the user leaves pcd as a logic "1", and attempts to perform an epp write, the chip is unable to perform the write (because pcd is a logic "1") and will appear to perform an epp read on the parallel bus, no error is indicated. epp 1.9 write the timing for a write operation (address or data) is shown in timing diagram epp write data or address cycle. iochrdy is driven active low at the start of each epp write and is released when it has been determined that the write cycle can complete. the write cycle can complete under the following circumstances: 1.if the epp bus is not ready (nwait is active low) when ndatastb or naddrstb goes active then the write can complete when nwait goes inactive high. 2.if the epp bus is ready (nwait is inactive high) then the chip must wait for it to go active low before changing the state of ndatastb, nwrite or naddrstb. the write can complete once nwait is determined inactive. write sequence of operation 1. the host selects an epp register, places data on the sdata bus and drives niow active. 2. the chip drives iochrdy inactive (low). 3. if wait is not asserted, the chip must wait until wait is asserted. 4. the chip places address or data on pdata bus, clears pdir, and asserts nwrite. 5. chip asserts ndatastb or naddrstrb indicating that pdata bus contains valid information, and the write signal is valid. 6. peripheral deasserts nwait, indicating that any setup requirements have been satisfied and the chip may begin the termination phase of the cycle. 7. a)the chip deasserts ndatastb or naddrstrb, this marks the beginning of the termination phase. if it has not already done so, the peripheral should latch the information byte now. b)the chip latches the data from the sdata bus for the pdata bus and asserts (releases) iochrdy allowing the host to complete the write cycle. 8. peripheral asserts nwait, indicating to the host that any hold time requirements have been satisfied and acknowledging the termination of the cycle. 9. chip may modify nwrite and npdata in preparation for the next cycle. epp 1.9 read the timing for a read operation (data) is shown in timing diagram epp read data cycle. iochrdy is driven active low at the start of each epp read and is released when it has been determined that the read cycle can complete. the read cycle can complete under the following circumstances: 1.if the epp bus is not ready (nwait is active low) when ndatastb goes active then the read can complete when nwait goes inactive high. 2.if the epp bus is ready (nwait is inactive high) then the chip must wait for it to go active low before changing the state of write or before ndatastb goes active. the read can complete once nwait is determined inactive.
112 read sequence of operation 1. the host selects an epp register and drives nior active. 2. the chip drives iochrdy inactive (low). 3. if wait is not asserted, the chip must wait until wait is asserted. 4. the chip tri-states the pdata bus and deasserts nwrite. 5. chip asserts ndatastb or naddrstrb indicating that pdata bus is tri-stated, pdir is set and the nwrite signal is valid. 6. peripheral drives pdata bus valid. 7. peripheral deasserts nwait, indicating that pdata is valid and the chip may begin the termination phase of the cycle. 8. a)the chip latches the data from the pdata bus for the sdata bus and deasserts ndatastb or naddrstrb. this marks the beginning of the termination phase. b)the chip drives the valid data onto the sdata bus and asserts (releases) iochrdy allowing the host to complete the read cycle. 9. peripheral tri-states the pdata bus and asserts nwait, indicating to the host that the pdata bus is tri-stated. 10. chip may modify nwrite, pdir and npdata in preparation for the next cycle.peripheral deasserts nwait, indicating that pdata is valid and the chip may begin the termination phase of the cycle. epp 1.7 operation when the epp 1.7 mode is selected in the configuration register, the standard and bi- directional modes are also available. if no epp read, write or address cycle is currently executing, then the pdx bus is in the standard or bi-directional mode, and all output signals (strobe, alf, init) are as set by the spp control port and direction is controlled by pcd of the control port. in epp mode, the system timing is closely coupled to the epp timing. for this reason, a watchdog timer is required to prevent system lockup. the timer indicates if more than 10 m sec have elapsed from the start of the epp cycle (nior or niow asserted) to the end of the cycle nior or niow deasserted). if a time-out occurs, the current epp cycle is aborted and the time-out condition is indicated in status bit 0. software constraints before an epp cycle is executed, the software must ensure that the control register bits d0, d1 and d3 are set to zero. also, bit d5 (pcd) is a logic "0" for an epp write or a logic "1" for and epp read. epp 1.7 write the timing for a write operation (address or data) is shown in timing diagram epp 1.7 write data or address cycle. iochrdy is driven active low when nwait is active low during the epp cycle. this can be used to extend the cycle time. the write cycle can complete when nwait is inactive high. write sequence of operation the host sets pdir bit in the control register to a logic "0". this asserts nwrite. the host selects an epp register, places data on the sdata bus and drives niow active. the chip places address or data on pdata bus. chip asserts ndatastb or naddrstrb indicating that pdata bus contains valid information, and the write signal is valid. if nwait is asserted, iochrdy is deasserted until the peripheral deasserts nwait or a time- out occurs. when the host deasserts niow the chip deasserts ndatastb or naddrstrb and latches the data from the sdata bus for the pdata bus.
113 chip may modify nwrite, pdir and npdata in preparation of the next cycle. epp 1.7 read the timing for a read operation (data) is shown in timing diagram epp 1.7 read data cycle. iochrdy is driven active low when nwait is active low during the epp cycle. this can be used to extend the cycle time. the read cycle can complete when nwait is inactive high. read sequence of operation 1 . the host sets pdir bit in the control register to a logic "1". this deasserts nwrite and tri-states the pdata bus. 2 . t he host selects an epp register and drives nior active. 3 . chip asserts ndatastb or naddrstrb indicating that pdata bus is tri-stated, pdir is set and the nwrite signal is valid. 4 . if nwait is asserted, iochrdy is deasserted until the peripheral deasserts nwait or a time-out occurs. 5 . the peripheral drives pdata bus valid. 6 . the peripheral deasserts nwait, indicating that pdata is valid and the chip may begin the termination phase of the cycle. 7 . when the host deasserts nior the chip deasserts ndatastb or naddrstrb. 8 . peripheral tri-states the pdata bus. 9 . chip may modify nwrite, pdir and npdata reparation of the next cycle. table 64 - epp pin descriptions epp signal epp name type epp description nwrite nwrite o this signal is active low. it denotes a write operation. pd<0:7> address/data i/o bi-directional epp byte wide address and data bus. intr interrupt i this signal is active high and positive edge triggered. (pass through with no inversion, same as spp). wait nwait i this signal is active low. it is driven inactive as a positive acknowledgement from the device that the transfer of data is completed. it is driven active as an indication that the device is ready for the next transfer. datastb ndata strobe o this signal is active low. it is used to denote data read or write operation. reset nreset o this signal is active low. when driven active, the epp device is reset to its initial operational mode. addrstb naddress strobe o this signal is active low. it is used to denote address read or write operation. pe paper end i same as spp mode. slct printer selected status i same as spp mode. nerr error i same as spp mode.
114 epp signal epp name type epp description pdir parallel port direction o this output shows the direction of the data transfer on the parallel port bus. a low means an output/write condition and a high means an input/read condition. this signal is normally a low (output/write) unless pcd of the control register is set or if an epp read cycle is in progress. note 1: spp and epp can use 1 common register. note 2: nwrite is the only epp output that can be over-ridden by spp con trol port during an epp cycle. for correct epp read cycles, pcd is required to be a low. extended capabilities parallel port ecp provides a number of advantages, some of which are listed below. the individual features are explained in greater detail in the remainder of this section. high performance half -duplex forward and reverse channel interlocked handshake, for fast reliable transfer optional single byte rle compression for improved throughput (64:1) channel addressing for low -cost peripherals maintains link and data layer separation permits the use of active output drivers permits the use of adaptive signal timing peer -to -peer capability vocabulary the following terms are used in this document: assert: when a signal asserts it transitions to a "true" state, when a signal deasserts it transitions to a "false" state. forward: host to peripheral communication. reverse: peripheral to host communication. pword: a port word; equal in size to the width of the isa interface. for this implementation, pw ord is always 8 bits. 1: a high level. 0: a low level. these terms may be considered synonymous: periphclk, nack hostack, nalf periphack, busy nperiphrequest, nfault nreverserequest, ninit
115 nackreverse, perror xflag, select ecpmode, nselectln hostclk, nstrobe reference document ieee 1284 extended capabilities port protocol and isa interface standard , rev 1.14, july 14, 1993. this document is available from microsoft. table 65 - bit map of the extended parallel port registers d7 d6 d5 d4 d3 d2 d1 d0 note data pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 ecpafifo addr/rl e address or rle field 2 dsr nbusy nack perror select nfault 0 0 0 1 dcr 0 0 direction ackinten selectin ninit alf strobe 1 cfifo parallel port data fifo 2 ecpdfifo ecp data fifo 2 tfifo test fifo 2 cnfga 0 0 0 1 0 0 0 0 cnfgb compres s intrvalue 0 0 0 0 0 0 ecr mode nerrintren dmaen serviceintr full empty note 1: these registers are available in all modes. note 2: all fifos use one common 16 byte fifo.
116 isa implementation standard this specification describes the standard isa interface to the extended capabilities port (ecp). all isa devices supporting ecp must meet the requirements contained in this section or the port will not be supported by microsoft. for a description of the ecp protocol, please refer to the ieee 1284 extended capabilities port protocol and isa interface standard , rev. 1.14, july 14, 1993. this document is available from microsoft. description the port is software and hardware compatible with existing parallel ports so that it may be used as a standard lpt port if ecp is not required. the port is designed to be simple and requires a small number of gates to implement. it does not do any "protocol" negotiation, rather it provides an automatic high burst -bandwidth channel that supports dma for ecp in both the forward and reverse directions. small fifos are employed in both forward and reverse directions to smooth data flow and improve the maximum bandwidth requirement. the size of the fifo is 16 bytes deep. the port supports an automatic handshake for the standard parallel port to improve compatibility mode transfer speed. the port also supports run length encoded (rle) decompression (required) in hardware. compression is accomplished by counting identical bytes and transmitting an rle byte that indicates how many times the next byte is to be repeated. decompression simply intercepts the rle byte and repeats the following byte the specified number of times. hardware support for compression is optional. table 66 - ecp pin descriptions name type description nstrobe o during write operations nstrobe registers data or address into the slave on the asserting edge (handshakes with busy). pdata 7:0 i/o contains address or data or rle data. nack i indicates valid data driven by the peripheral when asserted. this signal handshakes with nalf in reverse. periphack (busy) i this signal deasserts to indicate that the peripheral can accept data. this signal handshakes with nstrobe in the forward direction. in the reverse direction this signal indicates whether the data lines contain ecp command information or data. the peripheral uses this signal to flow control in the forward direction. it is an "interlocked" handshake with nstrobe. periphack also provides command information in the reverse direction. perror (nackreverse) i used to acknowledge a change in the direction the transfer (asserted = forward). the peripheral drives this signal low to acknowledge nreverserequest. it is an "interlocked" handshake with nreverserequest. the host relies upon nackreverse to determine when it is permitted to drive the data bus. select i indicates printer on line.
117 name type description nalf (hostack) o requests a byte of data from the peripheral when asserted, handshaking with nack in the reverse direction. in the forward direction this signal indicates whether the data lines contain ecp address or data. the host drives this signal to flow control in the reverse direction. it is an "interlocked" handshake with nack. hostack also provides command information in the forward phase. nfault (nperiphrequest) i generates an error interrupt when asserted. this signal provides a mechanism for peer -to -peer communication. this signal is valid only in the forward direction. during ecp mode the peripheral is permitted (but not required) to drive this pin low to request a reverse transfer. the request is merely a "hint" to the host; the host has ultimate control over the transfer direction. this signal would be typically used to generate an interrupt to the host cpu. ninit o sets the transfer direction (asserted = reverse, deasserted = forward). this pin is driven low to place the channel in the reverse direction. the peripheral is only allowed to drive the bi -directional data bus while in ecp mode and hostack is low and nselectin is high. nselectin o always deasserted in ecp mode. register definitions the register definitions are based on the standard ibm addresses for lpt. all of the standard printer ports are supported. the additional registers attach to an upper bit decode of the standard lpt port definition to avoid conflict with standard isa devices. the port is equivalent to a generic parallel port interface and may be operated in that mode. the port registers vary depending on the mode field in the ecr. the table below lists these dependencies. operation of the devices in modes other that those specified is undefined. table 67 - ecp register definitions name address (note 1) ecp modes function data +000h r/w 000-001 data register ecpafifo +000h r/w 011 ecp fifo (address) dsr +001h r/w all status register dcr +002h r/w all control register cfifo +400h r/w 010 parallel port data fifo ecpdfifo +400h r/w 011 ecp fifo (data) tfifo +400h r/w 110 test fifo cnfga +400h r 111 configuration register a cnfgb +401h r/w 111 configuration register b ecr +402h r/w all extended control register note 1: these addresses are added to the parallel port base address as selected by configuration register or jumpers. note 2: a ll addresses are qualified with aen. refer to the aen pin definition.
118 table 68 - extended control register mode descriptions mode description* 000 spp mode 001 ps/2 parallel port mde 010 parallel port data fifo mode 011 ecp parallel port mode 100 epp mode (if this option is enabled in the configuration registers) 101 (reserved) 110 test mode 111 configuration mode *refer to ecr register description data and ecpafifo port address offset = 00h modes 000 and 001 (data port) the data port is located at an offset of '00h' from the base address. the data register is cleared at initialization by reset. during a write operation, the data register latches the contents of the data bus on the rising edge of the niow input. the contents of this register are buffered (non inverting) and output onto the pd0 - pd7 ports. during a read operation, pd0 - pd7 ports are read and output to the host cpu. mode 011 (ecp fifo - address/rle) a data byte written to this address is placed in the fifo and tagged as an ecp address/rle. the hardware at the ecp port transmitts this byte to the peripheral automatically. the operation of this register is ony defined for the forward direction (direction is 0). refer to the ecp parallel port forward timing diagram, located in the timing diagrams section of this data sheet . device status register (dsr) address offset = 01h the status port is located at an offset of '01h' from the base address. bits 0 -2 are not implemented as register bits, during a read of the printer status register these bits are a low level. the bits of the status port are defined as follows: bit 3 nfault the level on the nfault input is read by the cpu as bit 3 of the device status register. bit 4 select the level on the select input is read by the cpu as bit 4 of the device status register.
119 bit 5 perror the level on the perror input is read by the cpu as bit 5 of the device status register. printer status register. bit 6 nack the level on the nack input is read by the cpu as bit 6 of the device status register. bit 7 nbusy the complement of the level on the busy input is read by the cpu as bit 7 of the device status register. device control register (dcr) address offset = 02h the control register is located at an offset of '02h' from the base address. the control register is initialized to zero by the reset input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low. bit 0 strobe - strobe this bit is inverted and output onto the nstrobe output. bit 1 alf - autofeed this bit is inverted and output onto the nalf output. a logic ?1? causes the printer to generate a line feed after each line is printed. a logic ?0? means no autofeed. bit 2 ninit - ninitiate output this bit is output onto the ninit output without inversion. bit 3 selectin this bit is inverted and output onto the nslctin output. a logic ?1? on this bit selects the printer; a logic ?0? means the printer is not selected. bit 4 ackinten - interrupt request enable the interrupt request enable bit when set to a high level may be used to enable interrupt requests from the parallel port to the cpu due to a low to high transition on the nack input. refer to the description of the interrupt under operation, interrupts. bit 5 direction if mode=000 or mode=010, this bit has no effect and the direction is always out regardless of the state of this bit. in all other modes, direction is valid and a logic 0 means that the printer port is in output mode (write); a logic ?1? means that the printer port is in input mode (read). bits 6 and 7 during a read are a low level, and cannot be written.
120 cfifo (parallel port data fifo) address offset = 400h mode = 010 bytes written or dmaed from the system to this fifo are transmitted by a hardware handshake to the peripheral using the standard parallel port protocol. transfers to the fifo are byte aligned. this mode is only defined for the forward direction. ecpdfifo (ecp data fifo) address offset = 400h mode = 011 bytes written or dmaed from the system to this fifo, when the direction bit is ?0?, are transmitted by a hardware handshake to the peripheral using the ecp parallel port protocol. transfers to the fifo are byte aligned. data bytes from the peripheral are read under automatic hardware handshake from ecp into this fifo when the direction bit is ?1?. reads or dmas from the fifo will return bytes of ecp data to the system. tfifo (test fifo mode) address offset = 400h mode = 110 data bytes may be read, written or dmaed to or from the system to this fifo in any direction. data in the tfifo will not be transmitted to the to the parallel port lines using a hardware protocol handshake. however, data in the tfifo may be displayed on the parallel port data lines. the tfifo will not stall when overwritten or underrun. if an attempt is made to write data to a full tfifo, the new data is not accepted into the tfifo. if an attempt is made to read data from an empty tfifo, the last data byte is re- read again. the full and empty bits must always keep track of the correct fifo state. the tfifo will transfer data at the maximum isa rate so that software may generate performance metrics. the fifo size and interrupt threshold can be determined by writing bytes to the fifo and checking the full and serviceintr bits. the writeintrthreshold can be derermined by starting with a full tfifo, setting the direction bit to ?0? and emptying it a byte at a time until serviceintr is set. this may generate a spurious interrupt, but will indicate that the threshold has been reached. the readintrthreshold can be derermined by setting the direction bit to ?1? and filling the empty tfifo a byte at a time until serviceintr is set. this may generate a spurious interrupt, but will indicate that the threshold has been reached. data bytes are always read from the head of tfifo regardless of the value of the direction bit. for example if 44h, 33h, 22h is written to the fifo, then reading the tfifo will return 44h, 33h, 22h in the same order as was written. cnfga (configuration register a) address offset = 400h mode = 111 this register is a read only register. when read, 10h is returned. this indicates to the system that this is an 8-bit implementation. (pword = 1 byte) cnfgb (configuration register b) address offset = 401h mode = 111
121 bit 7 compress this bit is read only. during a read it is a low level. this means that this chip does not support hardware rle compression. it does support hardware de-compression! bit 6 intrvalue returns the value on the isa irq line to determine possible conflicts. bits 5:0 reserved during a read are a low level. these bits cannot be written. ecr (extended control register) address offset = 402h mode = all this register controls the extended ecp parallel port functions. bits 7 - 5 these bits are read/write and select the mode. bit 4 nerrintren read/write (valid only in ecp mode) 1: disables the interrupt generated on the asserting edge of nfault. 0: enables an interrupt pulse on the high to low edge of nfault. note that an interrupt will be generated if nfault is asserted (interrupting) and this bit is written from a 1 to a 0. this prevents interrupts from being lost in the time between the read of the ecr and the write of the ecr. bit 3 dmaen read/write 1: enables dma (dma starts when serviceintr is 0). 0: disables dma unconditionally. bit 2 serviceintr read/write 1: disables dma and all of the service interrupts. 0: enables one of the following 3 cases of interrupts. once one of the 3 service interrupts has occurred serviceintr bit shall be set to a 1 by hardware. it must be reset to 0 to re-enable the interrupts. writing this bit to a 1 will not cause an interrupt. case dmaen=1: during dma (this bit is set to a ?1? when terminal count is reached). case dmaen=0 direction=0: this bit shall be set to 1 whenever there are writeintrthreshold or more bytes free in the fifo. case dmaen=0 direction=1: this bit shall be set to 1 whenever there are readintrthreshold or more valid bytes to be read from the fifo. bit 1 full read only 1: the fifo cannot accept another byte or the fifo is completely full. 0: the fifo has at least 1 free byte. bit 0 empty read only 1: the fifo is completely empty. 0: the fifo contains at least 1 byte of data.
122 table 69 - extended control register r/w mode 000: standard parallel port mode . in this mode the fifo is reset and common collector drivers are used on the control lines (nstrobe, nalf, ninit and nselectin). setting the direction bit will not tri -state the output drivers in this mode. 001: ps/2 parallel port mode. same as above except that direction may be used to tri -state the data lines and reading the data register returns the value on the data lines and not the value in the data register. all drivers have active pull -ups (push -pull). 010: parallel port fifo mode. this is the same as 000 except that bytes are written or dmaed to the fifo. fifo data is automatically transmitted using the standard parallel port protocol. note that this mode is only useful when direction is 0. all drivers have active pull -ups (push -pull). 011: ecp parallel port mode. in the forward direction (direction is 0) bytes placed into the ecpdfifo and bytes written to the ecpafifo are placed in a single fifo and transmitted automatically to the peripheral using ecp protocol. in the reverse direction (direction is 1) bytes are moved from the ecp parallel port and packed into bytes in the ecpdfifo. all drivers have active pull -ups (push -pull). 100: selects epp mode: in this mode, epp is selected if the epp supported option is selected in configuration register l3-crf0. all drivers have active pull -ups (push -pull). 101: reserved r/w mode 110: test mode. in this mode the fifo may be written and read, but the data will not be transmitted on the parallel port. all drivers have active pull -ups (push -pull). 111: configuration mode. in this mode the confga, confgb registers are accessible at 0x400 and 0x401. all drivers have active pull -ups (push -pull).
123 operation mode switching/software control software will execute p1284 negotiation and all operation prior to a data transfer phase under programmed i/o control (mode 000 or 001). hardware provides an automatic control line handshake, moving data between the fifo and the ecp port only in the data transfer phase (modes 011 or 010). setting the mode to 011 or 010 will cause the hardware to initiate data transfer. if the port is in mode 000 or 001 it may switch to any other mode. if the port is not in mode 000 or 001 it can only be switched into mode 000 or 001. the direction can only be changed in mode 001. once in an extended forward mode the software should wait for the fifo to be empty before switching back to mode 000 or 001. in this case all control signals will be deasserted before the mode switch. in an ecp reverse mode the software waits for all the data to be read from the fifo before changing back to mode 000 or 001. since the automatic hardware ecp reverse handshake only cares about the state of the fifo it may have acquired extra data which will be discarded. it may in fact be in the middle of a transfer when the mode is changed back to 000 or 001. in this case the port will deassert nalf independent of the state of the transfer. the design shall not cause glitches on the handshake signals if the software meets the constraints above. ecp operation prior to ecp operation the host must negotiate on the parallel port to determine if the peripheral supports the ecp protocol. this is a somewhat complex negotiation carried out under program control in mode 000. after negotiation, it is necessary to initialize some of the port bits. the following are required: set direction = 0, enabling the drivers. set strobe = 0, causing the nstrobe signal to default to the deasserted state. set alf= 0, causing the nalf signal to default to the deasserted state. set mode = 011 (ecp mode) ecp address/rle bytes or data bytes may be sent automatically by writing the ecpafifo or ecpdfifo respectively. note that all fifo data transfers are byte wide and byte aligned. address/rle transfers are byte -wide and only allowed in the forward direction. the host may switch directions by first switching to mode = 001, negotiating for the forward or reverse channel, setting direction to ?1? or ?0?, then setting mode = 011. when direction is 1 the hardware shall handshake for each ecp read data byte and attempt to fill the fifo. bytes may then be read from the ecpdfifo as long as it is not empty. ecp transfers may also be accomplished (albeit slowly) by handshaking individual bytes under program control in mode = 001, or 000. termination from ecp mode termination from ecp mode is similar to the termination from nibble/byte modes. the host is permitted to terminate from ecp mode only in specific well -defined states. the termination can only be executed while the bus is in the forward direction. to terminate while the channel is in the reverse direction, it must first be transitioned into the forward direction.
124 command/data ecp mode supports two advanced features to improve the effectiveness of the protocol for some applications. the features are implemented by allowing the transfer of normal 8 bit data or 8 bit commands. when in the forward direction, normal data is transferred when hostack is high and an 8 bit command is transferred when hostack is low. the most significant bit of the command indicates whether it is a run -length count (for compression) or a channel address. when in the reverse direction, normal data is transferred when periphack is high and an 8 bit command is transferred when periphack is low. the most significant bit of the command is always ?0?. reverse channel addresses are seldom used and may not be supported in hardware. table 70 - forward channel commands (hostack low) & reverse channel commands (peripack low) d7 d[6:0] 0 run -length count (0 -127) (mode 0011 0x00 only) 1 channel address (0 -127) data compression the ecp port supports run length encoded (rle) decompression in hardware and can transfer compressed data to a peripheral. run length encoded (rle) compression in hardware is not supported. to transfer compressed data in ecp mode, the compression count is written to the ecpafifo and the data byte is written to the ecpdfifo. compression is accomplished by counting identical bytes and transmitting an rle byte that indicates how many times the next byte is to be repeated. decompression simply intercepts the rle byte and repeats the following byte the specified number of times. when a run -length count is received from a peripheral, the subsequent data byte is replicated the specified number of times. a run -length count of zero specifies that only one byte of data is represented by the next data byte, whereas a run -length count of 127 indicates that the next byte should be expanded to 128 bytes. to prevent data expansion, however, run -length counts of zero should be avoided. pin definition the drivers for nstrobe, nalf, ninit and nselectin are open-collector in mode 000 and are push-pull in all other modes. isa connections the interface can never stall causing the host to hang. the width of data transfers is strictly controlled on an i/o address basis per this specification. all fifo -dma transfers are byte wide, byte aligned and end on a byte boundary. (the pword value can be obtained by reading configuration register a, cnfga, described in the next section.) single byte wide transfers are always possible with standard or ps/2 mode using program control of the control signals. interrupts the interrupts are enabled by serviceintr in the ecr register. serviceintr = 1 disables the dma and all of the service interrupts.
125 serviceintr = 0 enables the selected inter rupt condition. if the interrupting condition is valid, then the interrupt is generated immediately when this bit is changed from a 1 to a 0. this can occur during programmed i/o if the number of bytes removed or added from/to the fifo does not cross the threshold. the interrupt generated is isa friendly in that it must pulse the interrupt line low, allowing for interrupt sharing. after a brief pulse low following the interrupt event, the interrupt line is tri -stated so that other interrupts may assert . an interrupt is generated when: 1 . for dma transfers: when serviceintr is ?0?, dmaen is 1 and the dma tc is received. 2 . for programmed i/o: a . when serviceintr is 0, dmaen is 0, direction is ?0? and there are writeintrthreshold or more free bytes in the fifo. also, an interrupt is generated when serviceintr is cleared to 0 whenever there are writeintrthreshold or more free bytes in the fifo. b . ( 1 ) when serviceintr is ?0?, dmaen is 0, direction is ?1? and there are readintrthreshold or more bytes in the fifo. (2) an interrupt is also generated when serviceintr is cleared to ?0? whenever there are readintrthreshold or more bytes in the fifo. 3 . when nerrintren is 0 and nfault transitions from high to low or when nerrintren is set from ?1? to ?0? and nfault is asserted. 4 . when ackinten is ?1? and the nack signal transitions from a low to a high. fifo operation the fifo threshold is set in the chip configuration registers. all data transfers to or from the parallel port can proceed in dma or programmed i/o (non-dma) mode as indicated by the selected mode. the fifo is used by selecting the parallel port fifo mode or ecp parallel port mode. (fifo test mode will be addressed separately.) after a reset, the fifo is disabled. each data byte is transferred by a programmed i/o cycle or pdrq depending on the selection of dma or programmed i/o mode. the following paragraphs detail the operation of the fifo flow control. in these descriptions, ranges from 1 to 16. the parameter fifothr, which the user programs, is one less and ranges from 0 to 15. a low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of the request for both read and write cases. the host must be very responsive to the service request. this is the desired case for use with a "fast" system. a high value of threshold (i.e. 12) is used with a "sluggish" system by affording a long latency period after a service request, but results in more frequent service requests. dma transfers dma transfers are always to or from the ecpdfifo, tfifo or cfifo. dma utilizes the standard pc dma services. to use the dma transfers, the host first sets up the direction and state as in the programmed i/o case. then it programs the dma controller in the host with the desired count and memory address. lastly it sets dmaen to ?1? and serviceintr to 0. the ecp requests dma transfers from the host by activating the pdrq pin. the dma will empty or fill the fifo using the appropriate direction and mode. when the terminal count in the dma controller is reached, an interrupt is generated and serviceintr is asserted, disabling dma. in order to prevent possible blocking of refresh requests dreq shall not be asserted for more than 32 dma cycles in a row. the fifo is enabled directly by asserting npdack and addresses need not be valid. pintr is generated when a tc is received. pdrq must not be asserted for more than 32 dma cycles in a row. after the 32nd cycle, pdrq must be kept unasserted until npdack is deasserted for
126 a minimum of 350nsec. (note: the only way to properly terminate dma transfers is with a tc.) dma may be disabled in the middle of a transfer by first disabling the host dma controller. then setting serviceintr to 1, followed by setting dmaen to ?0?, and waiting for the fifo to become empty or full. restarting the dma is accomplished by enabling dma in the host, setting dmaen to ?1?, followed by setting serviceintr to 0. dma mode - transfers from the fifo to the host (note: in the reverse mode, the peripheral may not continue to fill the fifo if it runs out of data to transfer, even if the chip continues to request more data from the peripheral.) the ecp activates the pdrq pin whenever there is data in the fifo. the dma controller must respond to the request by reading data from the fifo. the ecp will deactivate the pdrq pin when the fifo becomes empty or when the tc becomes true (qualified by npdack), indicating that no more data is required. pdrq goes inactive after npdack goes active for the last byte of a data transfer (or on the active edge of nior, on the last byte, if no edge is present on npdack). if pdrq goes inactive due to the fifo going empty, then pdrq is active again as soon as there is one byte in the fifo. if pdrq goes inactive due to the tc, then pdrq is active again when there is one byte in the fifo, and serviceintr has been re-enabled. (note: a data underrun may occur if pdrq is not removed in time to prevent an unwanted cycle). programmed i/o mode or non-dma mode the ecp or parallel port fifos may also be operated using interrupt driven programmed i/o. software can determine the writeintrthreshold, readintrthreshold, and fifo depth by accessing the fifo in test mode. programmed i/o transfers are to the ecpdfifo at 400h and ecpafifo at 000h or from the ecpdfifo located at 400h, or to/from the tfifo at 400h. to use the programmed i/o transfers, the host first sets up the direction and state, sets dmaen to 0 and serviceintr to 0. the ecp requests programmed i/o transfers from the host by activating the pintr pin. the programmed i/o will empty or fill the fifo using the appropriate direction and mode. note: a threshold of 16 is equivalent to a threshold of 15. these two cases are treated the same. programmed i/o - transfers from the fifo to the host in the reverse direction an interrupt occurs when serviceintr is 0 and readintrthreshold bytes are available in the fifo. if at this time the fifo is full it can be emptied completely in a single burst, otherwise readintrthreshold bytes may be read from the fifo in a single burst. readintrthreshold = (16-) data bytes in fifo an interrupt is generated when serviceintr is 0 and the number of bytes in the fifo is greater than or equal to (16-). (if the threshold = 12, then the interrupt is set whenever there are 4-16 bytes in the fifo.) the pint pin can be used for interrupt-driven systems. the host must respond to the request by reading data from the fifo. this process is repeated until the last byte is transferred out of the fifo. if at this time the fifo is full, it can
127 be completely emptied in a single burst, otherwise a minimum of (16-) bytes may be read from the fifo in a single burst. programmed i/o - transfers from the host to the fifo in the forward direction an interrupt occurs when serviceintr is 0 and there are writeintrthreshold or more bytes free in the fifo. at this time if the fifo is empty it can be filled with a single burst before the empty bit needs to be re -read. otherwise it may be filled with writeintrthreshold bytes. writeintrthreshold = (16-) free bytes in fifo an interrupt is generated when serviceintr is 0 and the number of bytes in the fifo is less than or equal to . (if the threshold = 12, then the interrupt is set whenever there are 12 or less bytes of data in the fifo.) the pint pin can be used for interrupt-driven systems. the host must respond to the request by writing data to the fifo. if at this time the fifo is empty, it can be completely filled in a single burst, otherwise a minimum of (16-) bytes may be written to the fifo in a single burst. this process is repeated until the last byte is transferred into thefifo.
128 parallel port interface multiplexor the parallel port physical interface (pppi) the parallel port physical interface (pppi) may be owned and controlled by any of threesources. the sources are detailed as follows: table 71 - parallel port multiplexing options pppi controlling source device description config register 0x25 bits[4:3] pp_ha 8051 the parallel port physical interface is configured as a spp mode bi-directional parallel port controlled directly by the 8051 through a set of memory mapped external ram registers. [x:x] 0 fdc the parallel port physical interface is configured as a standard floppy disk drive interface. all configuration and control bits pertaining to the fdc logical device apply to the pppi in this mode [1:0] or [0:1] 1 host the parallel port physical interface is configured as the legacy parallel port which supports compatible, spp, epp and ecp modes of operation. all configuration and control bits pertaining to the parallel port logical device apply to the pppi in this mode. [0:0] or [1:1] 1 when the host (parallel port logical device) owns/controls the parallel port interface, its state (i.e., pwrdown) determines the states of the pins. when the fdc (fdc logical device) owns/controls the parallel port interface, its state (i.e., powerdown) determines the state of the pins. when the 8051 controls/owns the parallel port interface, it has direct control of the parallel port physical interface pins. under 8051 control the parallel port output pins are always enabled or driven and only tri-state when vcc2 is removed (powergood=0). if the host does not have control of the parallel port physical interface (pppi), then it is left as a function of the software driver or bios to de- activate the drq and irq of the parallel port logical device by either setting its dma channel select configuration register to 0x04 and its interrupt select configuration regsiter to 0x00 or by clearing the parallel port logical device?s activate bit. also, if the host does not have control of the pppi, then the following parallel port logical device registers are read as follows. data register (read) = last data register (write). control register (read): read as ?cable not connected? [strobe, lf, and slc = 0 and ninit = 1. status register (read): nbusy, pe, slct = 0, nack, nerr = 1.
129 note: bit d7 of the 8051 memory mapped disable register (parallel port enable bit) has no effect on the parallel port physical interface pins when the port is owned by any source other than the the host (parallel port logical device). host (legacy) parallel port interface (FDC37N972 standard) in this mode, the parallel port pins are controlled by the host through the parallel port logical device. refer to the configuration section and the parallel port section for information on the configuration and control registers respectively. parallel port fdc interface in this mode, the floppy disk control signals are available on the parallel port pins. when this mode is selected, the parallel port is not available to the host. parallel port fdc pin out the fdc signals are muxed onto the ?parallel port pins as shown in the following table. outputs are od14, open drain which sink 14ma. table 72 - parallel port floppy pin out parallel port spp mode fdc mode connector pin # signal name pin direction signal name pin direction 1 nstrobe i/o nds0 (o)* 2 pd0 i/o nindex i 3 pd1 i/o ntrk0 i 4 pd2 i/o nwp i 5 pd3 i/o nrdata i 6 pd4 i/o ndskchg i 7 pd5 i/o - - 8 pd6 i/o nmtr0 (o)* 9 pd7 i/o - - 10 nack i nds1 (o)* 11 busy i nmtr1 (o)* 12 pe i nwdata o 13 slct i nwgate o 14 nalf i/o drvden0 o 15 nerr i nhdsel o 16 ninit i/o ndir o 17 nslctin i/o nstep o *these pins are outputs in mode ppfd2; in mode ppfd1 only one pair, depending on drive swap bit, is active and should be connected to the fdd, the inactive pair should not be connected to the fdd.
130 parallel port fdc control there are two modes of operation, ppfd1 and ppfd2. these modes can be selected in global configuration register 0x25 (device mode), bits 3 and 4. ppfd1 mode has only drive 1 on the parallel port pins; ppfd2 mode has drive 0 and 1 on the parallel port pins. note: the drive swap bit, fdd mode configuration register bit-4 (ld0_crf0), can be used to swap the motor and drive select outputs on of the parallel port fdc. table 73 - parallel port fdc modes of operation ppfd1: drive 0 is on the fdc pins. drive 1 is on the parallel port pins. drive swap bit = 0 drive 1 is on the fdc pins. drive 0 is on the parallel port pins. drive swap bit = 1 ppfd2: drive 0 is on the parallel port pins. drive 1 is on the parallel port pins. the following fdc output pins are open drain 14ma outputs when the parallel port fdc is selected by the drive select register. reminder, it is up to the designer to provide pull-up resistors on these fdc output pins. nwdata, drvden0, nhdselm nwgate, ndir, nstep, nds1, nds0, nmtr0, nmtr1.
131 parallel port - 8051 control in this mode, the parallel port pins are controlled by the 8051 through a set of three on-chip memory mapped registers. the memory mapped registers are the par port status, the par port control, and the par port data registers. in this mode, the parallel port pins are not controlled by the parallel port logical device. refer to the 8051 section of this specification for information on these control registers. table 74 - fdc on parallel port activation control fdc parallel port mode cr25 bits [4:3] fdc active bit l0-cr30-bit0 fdc in power down parallel port active bit parallel port in power down pp_ ha parallel port pins (mode) state 01 or 10 0 x x x 1 (fdc) inactive 01 or 10 1 n x x 1 (fdc) active 01 or 10 1 y x x 1 (fdc) inactive 00 or 11 x x 0 x 1 (parallel port) inactive 00 x x 1 n 1 (parallel port) active 00 x x 1 y 1 (parallel port) inactive 00 x x x x 0 (8051 mode) active i nactive = h i - z on pins active = od14/o14 as per selected mode. the fdd pins that are multiplexed onto the parallel port function independently of the state of the parallel port logical device. this affects the pins when cr25 bits [4:3] are 01 or 10. (note: fdc mode bits l0-crf0-b[7:6] have no effect on the parallel port pins). auto power management auto power management (apm) capabilities are provided for the following logical devices: floppy disk, uart, infrared and the parallel port. for each logical device, two types of power management are provided; direct powerdown and auto powerdown. system power management see the ?8051 system power management? section for details. fdc power management direct power management is controlled through global configuration register 22 (cr22). refer to cr22 in the configuration section for more information. auto power management is enabled through bit- 0 of cr23. when set, this bit allows the fdc to enter powerdown when all of the following conditions have been met: 1.the motor enable pins of the fdc?s dor register are inactive (zero). 2.the FDC37N972 must be idle; the msr register = 80h and the fdc?s interrupt = 0 (int may be high even if msr = 80h due to polling interrupts). 3.the head unload timer must have expired. 4.the auto powerdown timer (10msec) must have timed out. an internal timer is initiated as soon as the auto powerdown command is enabled. the
132 FDC37N972 is then powered down when all the conditions are met. disabling the auto powerdown mode cancels the timer and holds the fdc block out of auto powerdown. dsr from powerdown bit 6 of the fdc?s dsr register is another fdc powerdown bit. if dsr powerdown is used when the FDC37N972 is in auto powerdown, the dsr power down will override the auto powerdown. however, when the FDC37N972 is awakened from dsr powerdown, the auto powerdown will once again become effective. wake up from auto powerdown if the FDC37N972 enters the powerdown state through the auto powerdown mode, then the FDC37N972 can be awakened by reset or by appropriate access to certain registers. if a hardware or software reset is used then the FDC37N972 will go through the normal reset sequence. if the access is through the selected registers, then the fdc resumes operation as though it was never in powerdown. besides activating the nreset_out pin or one of the software reset bits in the dor or dsr registers, the following register accesses will wake up the FDC37N972: 1. seting any one of the motor enable bits in the dor register (reading the dor does not awaken the FDC37N972). 2. a read from the msr register. 3. a read from or a write to the data register. once awake, the fdc will reinitiate the auto powerdown timer for 10 ms. the FDC37N972 will powerdown again when all the powerdown conditions are satisfied. register behavior table 75 shows the at and ps/2 (including model 30) configura tion registers available. it also shows the type of access permitted. in order to maintain software transparency, access to all the registers is maintained. as table 75 shows, two sets of registers are distinguished based on whether their access results in the FDC37N972 remaining in powerdown state or exiting it. access to all other registers is possible without awakening the FDC37N972. these registers can be accessed during powerdown without changing the status of the FDC37N972. a read from these registers will reflect the true status as shown in the register description in the fdc section. writes to these registers will result in the FDC37N972 retaining the data and subsequently reflecting it when the FDC37N972 awakens. access ing the FDC37N972 during powerdown may cause an increase in the power consumption by the FDC37N972. the FDC37N972 will revert back to its low power mode when the access has been completed. pin behavior the FDC37N972 is specifically designed for portable pc systems in which power conservation is a primary concern. this makes the behavior of the pins during powerdown very important. the pins which interface to the floppy disk drive are disabled so that no power will be drawn through the FDC37N972 as a result of any voltage applied to the pin within the vcc2 power supply range. most of the pins that interface to the system are left active to monitor system accesses that may wake up the FDC37N972.
133 system interface pins table 76 gives the state of the system interface pins in the powerdown state. pins unaffected by the powerdown are labeled "unchanged". input pins are "disabled" to prevent them from causing currents internal to the FDC37N972 when they have indeterminate input values. table 75 - pc/at and ps/2 available registers base + address available registers access permitted pc/at ps/2 (model 30) access to these registers does not wake up the FDC37N972 00h ---- sra r 01h ---- srb r 02h dor (1) dor (1) r/w 03h --- --- --- 04h dsr (1) dsr (1) w 06h --- --- --- 07h dir dir r 07h ccr ccr w access to these registers wakes up the FDC37N972 04h msr msr r 05h data data r/w note 1: writing to the dor or dsr does not wake up the FDC37N972, however, writing any of the motor enable bits or doing a software reset (via dor or dsr reset bits) will wake up the FDC37N972. t able 76 - state of system pins in fdc auto powerdown system pins state in auto powerdown input pins nior unchanged niow unchanged aen unchanged nmemrd unchanged nmemwr unchanged sa[15:0] unchanged sd[7:0] unchanged nnows unchanged(hi-z) ndackx unchanged tc unchanged nromcs unchanged output pins nreset_out unchanged irqx unchanged(low) db[0:7] unchanged drqx unchanged(low) iochrdy unchange(n/a)
134 fdd interface pins all pins in the fdd interface, which can be connected directly to the floppy disk drive itself, are either disabled or tristated. pins used for local logic control or part programming are unaffected. table 77 depicts the state of the floppy disk drive interface pins in the powerdown state. fdd power down pin (fpd) behavior the fpd pin can be used to automatically shut off power to the floppy disk drive when it is not required. the fpd pin is an active high output signal that is driven based on the states of the fdc. whenever the fdc shutdown bit is set (see fdd mode register, bit-5 in the configuration register section) the fpd pin goes high. if the fdc shutdown bit is not set then the fpd pin will go high whenever the fdc bit (see bit 0 of the power mgmt register in the configuration section) is set and the fdc has entered an auto powerdown state as described above. if neither the fdc shutdown bit nor the fdc bit are set then the fpd pin goes active ?high? when the power- down bit is set (see bit 6 of the data rate select register [dsr]) and ?low? when the powerdown bit is cleared. refer to table 78 - fdd power down pin behavior . table 77 - state of floppy disk drive interface pins in fdc powerdown fdd pins state in fdc auto powerdown input pins nrdata input nwprot input ntrk0 input nindex input ndskchg input output pins nmtr[1:0] tristated nds[1:0] tristated ndir active nstep active nwdata tristated wgate tristated nhdsel active drvden[1:0] active fpd active
135 table 78 - fdd power down pin behavior power down bit, dsr, bit-6 fdc bit, gcr23 bit-0 auto power down fdc shutdown bit, fdd mode register fpd pin state 0 0 0 0 power down bit, dsr, bit-6 fdc bit, gcr23 bit-0 auto power down fdc shutdown bit, fdd mode register fpd pin state 1 0 0 1 x 1 0 1 (note) x x 1 1 note: the fpd pin will go active when the fdc auto powers down. refer to the fdc auto power management section for more details. uart power management direct power management is controlled by cr22. refer to cr22 in the configuration section for more information. auto power management is enabled by cr23 bit 4 and bit 5. when set, these bits allow the following auto power management operations: 1.the transmitter enters auto powerdown when the transmit buffer and shift register are empty. 2.the receiver enters powerdown when the following conditions are all met: a. receive fifo is empty b. the receiver is waiting for a start bit note: while in powerdown the ring indicator interrupt is still valid. exit auto powerdown the transmitter exits powerdown on a write to the transmit buffer. the receiver exits auto powerdown when rxd changes state. parallel port power management direct power management is controlled by cr22. refer to cr22 in the configuration section for more information. auto power management is enabled by cr23 bit 3. when set, this bit allows the ecp or epp logical parallel port blocks to be placed into powerdown when not being used. the epp logic is in powerdown under any of the following conditions: epp is not enabled in the configuration registers. epp is not selected through ecr while in ecp mode. the ecp logic is in powerdown under any of the following conditions: ecp is not enabled in the configuration registers. spp, ps/2 parallel port or epp mode is selected through ecr while in ecp mode. xit auto powerdown the parallel port logic can change powerdown modes when the ecp mode is changed through the ecr register or when the parallel port mode is changed through the configuration registers.
136 8051 embedded controller 8051 functional overview the high-performance 8051 embedded controller is a fully static cmos core compatible with the industry- standard 80c51 microcontroller. the high-performance 8051 features include: 2.5x average instruction execution speed improvement over the entire instruction set; i.e., typical 4-clock instruction cycle in high- performance 8051 vs. 12-clock instruction cycle in standard 8051. faster clock speed: 24mhz or higher vs. 16mhz in standard 8051. dual data pointers more interrupts: power-fail, external interrupt 2, external interrupt 3, etc. a set of external memory/mapped control registers provides the 80c51 core with the ability to directly control many functional blocks of the FDC37N972. this section concentrates on the FDC37N972 enhancements to the 80c51. for non-standard special function registers, interrupt processing and timer 2 functions see appendix b. for general information about the 80c51, refer to the hardware description of the 8051, 8052, and 80c51 and the 80c51bh-1/80c51bh-2 chmos single-chip 8 bit microcomputer data sheets in the 8 bit embedded controller handbook. features 16x32k external rom 256 byte internal scratch rom 256 bytes internal ram 256 bytes of external ram 256 byte external memory/mapped control register area 128 byte special function register area access to 256 byte rtc cmos ram 8042 style keyboard controller host interface eleven interrupt sources watch dog timer (wdt) ring oscillator with fail safe control high-performance 8051 implemented features there are five significant features implemented in the high-performance 8051 core. these features, summarized in table 79 , are described more fully in the sub-sections that follow. table 79 - high-performance 8051 implemented features feature value description internal ram size 256 (bytes) the internal ram size is 256 bytes to maintain compatibility with existing implementations. internal timers (note) 3 there are three internal timers (t0, t1 & t2). internal rom size 2048 (bytes) the internal rom size is 2048 bytes to maintain compatibility with existing implementations. serial ports 1 there is one serial port. interrupts 11 the high-performance 8051 interrupt unit provides 11 interrupt sources (see table 92 ). note: the external inputs for timer/counter t0, t1, and t2, as well as the timer/cou nter 2 capture/reload trigger t2ex are not supported in the FDC37N972.
137 functional blocks below are the functional blocks that the 8051 core has control of through its on-chip memory/mapped external registers. 8042 style keyboard controller interface extended interrupts power management functions direct keyboard scan matrix (up to 128 keys) four channel ps/2 interface dual access bus interface led controls two pulse width modulators rtc cmos ram access 8051 control of the parallel port interface 42 general purpose i/o (gpio) pins acpi embedded controller pm1 block high-performance 8051 cycle timing and instruction set the high-performance 8051 processor offers increased performance by executing instructions in a 4-clock cycle, as opposed to the standard 8051. the shortened bus timing improves the instruction execution rate for most instructions by a factor of three over the standard 8051 architectutres. some instructions require a different number of instruction cycles on the high-performance 8051than they do on the standard 8051. in the standard 8051, all instructions except for mul and div take one or two instruction cycles to complete. in the high-performance 8051 architecture, instructions can take between one and five instructions to complete. the average speed improvement for the entire instruction set is approximately 2.5x. see table 253 - 8051 instruction set on page 380 for number of cycles on individaul instruction requries. powering up or resetting the 8051 default reset conditions the FDC37N972 has two sources of reset: a vcc1 power on reset (vcc1 por) or a vcc2 por. an FDC37N972 reset from any of these sources will cause the hardware response shown in table 86 , 8051 on-chip external memory mapped registers. note that the values shown are those prior to any resident firmware control. refer to table 86 for the effect of each type of reset on each of the on- chip registers. power-up sequence when the 8051 first powers up by vcc1, the ring oscillator is started, once this has stabilized, the 8051 starts executing from program address 00. once running, the 8051 can access all of the registers that are on vcc1 and if vcc2 is at 3.3v it can access all of the registers on vcc2. for on-chip registers powered by vcc1 which are reset upon vcc2 power on reset (vcc2 por), it is important that 8051 firmware not initialize or write to any of these registers until 1ms following vcc2 = 3.3v and pwrgd = 1 (see table 86 .) note: in order to guarantee that the external flash device has powered up and is ready to operate before the 8051 attempts to access it, the internal vcc1 por pulse has been extended to 20ms. the internal vcc1 por signal is asserted upon vcc1 reaching a valid level and will remain asserted for a period of 20ms following the assertion of the vcc1_pwrgd pin.
138 figure 10 - system power up sequence ring oscillator is started once the ring oscillator has stabilized, the 8051 is held in reset for the required number of clock cycles and then released. no power to system (vcc0, vcc1, vcc2 off) vcc0, vcc1 on; vcc2 off nea = 0 ? n the 8051 begins executing from program address 00h. y the 8051 begins executing code at address 8000h. vcc1 powered registers are reset to their vcc1 por values. ireset_out bit forced high and latched by the FDC37N972 hardware
139 system reset sequence system is running (vcc2 on, vcc1 on) 8051 executing keyboard firmware. 8051 programs the stop clock counter stp_cnt[3:0] <- x stop-clock cnt = 0 ? y n 8051 releases the system reset (ireset_out register bit is reset) 8051 goes into idle mode nreset_out de-asserted host resets 8051stp_clk bit nreset_out = high & 8051stp_clk = 1 cause 8051 clock to stop host now owns flash interface, shadows flash to ram 8051 wakes up from idle mode and starts executing from where it left off (note 1) nreset_out pin 8051 timer irq ? y n (note 2) note 2: in order to leave idle mode the 8051 must receive an interrupt; typically a software timer interrupt will be used. note1: ireset_out being reset to 0 (toggling from 1 to 0) 1) sets 8051stp_clk[0]=1 2) sets hmem[7:0]=03h and 3) causes the stopclock counter to start counting down somehow a reset event is conveyed to the 8051. command from host and/or directly from a gpi/o type pin transition? 8051 asserts ireset_out nreset_out pin figure 11 - typical system reset sequence
140 cpu reset sequence often the host cpu (x486 or pentium) is reset by the hardware signal, cpu_reset, which is issued by software to switch the processor from protected, or ?virtual 86?, mode back to real mode. cpu_reset can be generated from the FDC37N972 8051 core or it may be generated from other logic on the pc motherboard. cpu_reset is meant only to reset the cpu; the rest of the system continues to run normally, including the keyboard bios in the 8051. reacting to the cpu_reset, the cpu performs a code fetch to a reset vector address that is located 16 bytes below the top address of memory (4gb - 16b). this generates an active nromcs to the FDC37N972 along with memory rd strobes, but since the 8051 has not passed control of the flash interface to the host cpu the FDC37N972 must supply a set of emulated cpu instructions that cause the cpu to jump to its shadowed boot vector address at (1mb - 16b). if the host does not have control of the flash when nromcs and nmemrd are simultaneously asserted, the FDC37N972 decodes the lower three system address bits, sa[2:0] and presents the host with 0xea on the system data bus sd[7:0] when sa[2:0] = 0, or 0xf0 otherwise (figure 12 ). this results in an opcode that instructs the host cpu to perform an absolute jump to address 0xffff0, where the bios is shadowed. note: the FDC37N972 cpu reset sequence described above is independent of the bonding option.
141 system vcc a2 a1 a0 nromcs nmemrd hstfl sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 system data bus sd[7:0] figure 12 - system reset boot vector
142 8051 clock controls clock sources external clock signal the external clock source is from a 14.318mhz ttl compatible clock. vcc2 must be powered in order for this to occur. internal clock signal the 8051 may program it self to run off of an internal ring oscillator having a frequency range between 4 and 12mhz. this is not a precise clock, but is meant to provide the 8051 with a clock source when vcc2 is shut down in the system. frequency controls the 8051 system clock frequencies are selected by the kbdclk[1:0] control bits in the kstp_clk register. the kstp_clk register is mmcr 0x7f27. in the kstp_clk register, the stp_cnt[3:0] bits are moved from the kstp_clk register to the stop_count register, the kbdclk enable bit and a reserved bit (possibly to control the 14.318 mhz pll power-down function) are added to the kstp_clk register. to ?stop? the 8051 clock, use the kbdclk enable bit d0 in the kstp_clk register ( table 81 ). table 80 - stop_count register host address 8051 address power plane default - 0x7f2f vcc1 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 type r r r r r/w r/w r/w r/w bit name reserved stp_cnt[3:0] stp_cnt[x] this defines the number of machine cycles from when the internal ireset_out bit is cleared until the external nreset_out pin goes inactive high (deasserts). the stp_cnt[3:0] bits are d0 ? d3 in the FDC37N972 kstp_clk register.
143 table 81 - kstp_clk register host address 8051 address power plane default - 0x7f27 vcc1 0x10 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 type r/w r/w r/w r/w r r r/w r/w bit name kbdclk[1:0] 1 kbclk/rosc roscen reserved pll_stop kbdclk enable kbdclk/enable when the kbdclk enable bit is ?0?, the 8051 pll clock is stopped, like when the kbdclk[1:0] = 0,0 in the fdc37c95x. when kbdclk enable is ?1?, the 8051 pll clock is running. pll_stop the pll_stop bit d1 is used to control the power state of the 14.318mhz pll. when the pll_stop bit is ?1? the pll and all of the internal clocks except for the rtc and ring oscillator are stopped. when the pll_stop bit is ?0? the pll and all of the internal clocks are running. when vcc2 is active and the pll_stop bit changes from ?1? to ?0?, there is a delay of 100 m s max. before the pll clocks are stable. roscen this bit reflects the state of the ring oscillator clock at all times. the 8051 can write this bit to start or stop the ring oscillator. other hardware events can also start or stop this clock. = 1 turn on ring oscillator = 0 turn off ring oscillator this bit is reset when the 8051 goes into ?sleep? mode and is set when the 8051 first wakes up from ?sleep? mode. kbclk/rosc this bit is used to control the clock source for the 8051. 1 = 8051 clock source is kbclk 0 = 8051 clock source is ring oscillator. this bit is reset when the 8051 just wakes up from the ?sleep? mode kbdclk[1:0] these 2 bits control the 8051 system clock frequencies.
144 table 82 - kbdclk control bit encoding kbdclk[1:0] control bits kstp_clk register kbd clock frequencies d7 d6 FDC37N972 0 0 12mhz 0 1 16mhz 1 0 24mhz 1 1 reserved 8051 ring oscillator fail-safe controls a fail-safe control for the 8051 ring oscillator is in the FDC37N972 as protection against unpredicted vcc2 power failures. the fail-safe ring oscillator sequence occurs as follows: 1. a vcc2 power-fail event is detected when the pwrgd pin changes from ?1? to ?0? ( figure 3 ? power-fail event ). 2. the power-fail event sequence starts the 8051 ring oscillator. the ring oscillator frequency range is the same as the fdc37c95x; i.e., 4mhz to 12mhz. 3. the 8051 system clock is switched to the ring oscillator. note: following a power fail event, vcc2 must be 3 3v and the 14.318mhz input clock clocki must remain stable for 10 m s min. ( figure 4 - vcc2 power-up timing ). 4. an 8051power-fail interrupt (pfi) is generated to inform the 8051 of the power fail event. there are four functional power-fail event scenarios. the actions taken for each are described in table 83 .
145 table 83 - power-fail event actions actions 8051 state assert pgi 1 assert ring osc. 2 assert 8051 flash access description 1 sleeping on ring osc. 3 - - no fail-safe actions taken 2 running on ring osc. 3 - - no fail-safe actions taken; 8051 can respond to pfi if needed. 3 running on pll 3 3 - internal pwrgd is delayed until ring osc. is asserted. 4 stopped on pll 3 3 3 internal pwrgd is delayed until ring osc. is asserted and the 8051 controls the flash. note 1: pgi is the powergood interrupt bit d0 in the pwrgd_int register (see power fail irq on page 184). note 2: the 8051 is switched to the ring oscillator after a delay. (see pwrgd and vcc1_pwrgd timing is illustrated in figure 3 ? power-fail event through figure 5 - vcc1_pwrgd timing ) 8051 memory map the FDC37N972 has two modes of rom support based on the bondout option. under alt bondout, the 8051 can address 2kb of internal rom, 256b of internal scratch rom, and up to 32k of external rom. when high, the nea pin is used to enable fetches to the 2k + 256b of internal rom and when low the nea pin diables fetches to internal rom access by routing them to external rom. the FDC37N972 also contains 256 bytes of internal on-chip ram. for alt bondout with nea=1, the internal rom is addressed from 0-7ff, all rom access from 800h-7fffh are invalid address locations. it can support up to 32k bytes of additional external code memory addressed as 8000h to ffffh by the 8051. this 32k can be mapped to any of the sixteen 32k memory block in the 512k external rom by the kmem register. under smsc bondout, the 8051 can address 256b of internal scratch rom and 32k of external rom. the nea pin is used to enable access to the 256b of internal scratch rom or external program rom. the FDC37N972 also contains 256 bytes of internal on-chip ram. under smsc bondout with nea=0, all the rom is addressed as the external rom. it can support up to 32k bytes of external code memory addressed as 00h to 7fffh (the addresses from 8000h to ffffh wrap to the same addresses as 00h to 7fffh). this 32k can be mapped to any of the sixteen 32k memory blocks in the 512k external rom by the
146 kmem register. at initial power-up (vcc1 por) the chip will execute from the block selected by the default value of the kmem register. the 8051 can access up to 32k bytes of external ram addressed from 0-7fffh. refer to table 86 for a list of the implemented on-chip memory mapped registers. external memory addressed from 8000h-ffffh will access the 32k bytes of program memory (8000-ffffh) selected by the kmem register. the 256 bytes of ram from 7e00h-7effh as well as the 256 bytes of scratch ram from 7d00h-7dffh are powered by vcc1. these are general purpose read/write registers available to the 8051. the scratch ram may be converted into scratch rom by setting the mmc bit. memory map configuration control bit the configuration register 0, an 8051 memory mapped register at address 7ff4h includes a bit called the memory map control bit (mmc). the mmc bit is bit-3 of this register and defaults to zero on vcc1 por. when mmc=0 the 8051 memory map will contain an additional 256 bytes of external scratch ram in the address range 7d00h through 7dffh. when mmc=1 the scratch ram at 7d00h-7dffh becomes scratch rom at 00h-0ffh (for an smsc bond out device) or scratch rom at 800h-8ffh (for an alt bond out device). the configuration register 0 register is described in the 8051 control register section of this specification. smsc/alt bond option [nea=0] regardless of the bonding option, if nea is held low the 8051 memory map for both options is the same as shown in the figure below.
147 program data external internal sfr (direct direct and indirect 00h 80h 7d00h 7e00h 7f00h 7fffh m/m ram scratch 8000h ffffh same 0000h - smsc / alt bondout, nea = 0, mmc external ffh 80h ffh figure 13 - 8051 memory map for any bond option with nea low instructions to access memory mov : internal ram/registers. movc : program rom from 0000h thr ough ffffh movx : external ram from 7d00h through 7fffh -and- external rom from 8000h through ffffh. (allows flashing of rom). smsc bond option [nea=1]
148 this section describes the 8051 memory map for an smsc bonded part where the nea pin is high. the mmc bit determines the configuration of the 8051?s memory map. when nea=1 an additional 256 of re-writable rom space can be added to the 8051?s internal rom space to allow patch code upgrades. in order to take advantage of this extra 256 bytes of scratch ram/rom certain design considerations must be met as outlined in the following programmers notes. mmc bit = 0 when the mmc bit is low (vcc1 por default) a hard coded long jump ljmp to 8000h is encoded at addresses 00h through 02h and a 256 byte scratch ram is located at external addresses 7d00-7dff. the encoding for the hard coded long jump is shown in the following table. hard coded ljmp to 8000h. 8051 address encoding 00h 02h 01h 80h 02h 00h program memory data memory external internal sfr (direct only) direct and indirect indirect only 00h 80h 7d00h 7e00h 7f00h 7fffh m/m registers ram scratch ram 8000h ffffh smc bondout, nea = 1, reg mmc bit = 0 hard coded internal 00h 02h 32k external ffh 80h ffh figure 14 - 8051 memory map for smc bond option with nea=1, mmc=0
149 instructions to access memory mov : internal ram/registers. movc : program rom from 8000h through ffffh movx : external ram from 7d00h through 7fffh -and- external rom from 8000h through ffffh. (allows flashing of rom). mmc bit = 1 when the mmc bit is high the scratch ram at 7d00h-7dffh is disabled and now becomes the executable internal scratch rom at address locations 00h-0ffh. the hard coded ljmp to 8000h is overrided by the scratch rom. program data external internal sfr (direct direct and indirect 00h 80h 7d00h 7e00h 7f00h 7fffh m/m ram scratch internal 8000h ffffh smsc bondout, nea = 1, mmc bit = 1 00h ffh 32k external ffh 80h ffh figure 15 - 8051 memory map for smc bond option with n ea=1, mmc=1 instructions to access memory mov : internal ram/registers. movc : program rom from 8000h through ffffh called from 00h-0ffh or from 8000h-0 ffffh. program rom from 00h through 0ffh called from 00h-0ffh only. movx : external ram from 7e00h through 7fffh -and- external rom from 8000h through ffffh. (allows flashing of rom).
150 alt bond option [nea=1] this section describes the 8051 memory map for an alt bonded part where the nea pin is high. the mmc bit determines the configuration of the 8051?s memory map. mmc bit = 0 when the mmc bit is low (vcc1 por default) an additional 256 bytes of scratch ram are added to the 8051?s memory map at addresses 7d00h though 7dffh. program memory data memory external internal sfr (direct only) direct and indirect indirect only 00h 80h 7d00h 7e00h 7f00h 7fffh m/m registers ram scratch ram 8000h ffffh alt bondout, nea = 1, mmc bit = 0 2k internal mask rom 00h 7ffh 32k external ffh 80h ffh figure 16 - 8051 memory map for alt bond option with nea=1, mmc=0 instructions to access memory mov : internal ram/registers. movc : program rom from 8000h through ffffh called from 00h-7ffh or f rom 8000h-0ffffh. program rom from 00h through 7ffh called from 00h-7ffh only. movx : external ram from 7d00h through 7fffh -and- external rom from 8000h through ffffh. (allows flashing of rom).
151 mmc bit = 1 when the mmc bit is high an additional 256 bytes of executable rom space between address 800h and 8ffh is added to the 8051?s internal rom space to allow patch code upgrades. program memory data memory external internal sfr (direct only) direct and indirect indirect only 00h 80h 7d00h 7e00h 7f00h 7fffh m/m registers ram 8000h ffffh alt bondout, nea = 1, mmc bit = 1 00h 32k external 2k internal mask rom 7ffh scratch rom internal 800h 8ffh ffh 80h ffh reserved 1000h figure 17 - 8051 memory map for alt bond option with n ea=1, mmc=1 instructions to access memory mov : internal ram/registers. movc : program rom from 8000h through ffffh called from 00h-8ffh or from 8000h-0ffffh. program rom from 00h through 8ffh called from 00h-8ffh only. movx : external ram from 7e00h through 7fffh -and- external rom from 8000h through ffffh. (allows flashing of rom).
152 flash rom interface overview the FDC37N972 supports a 512k byte flash rom interface (see host boot block select on page 195.) a high-order address bit fa18 is added to the FDC37N972 on gpio13 (see table 4 for a description of the alternate function pins and multifunction pin on page 271). a chip enable output nfcs for the flash rom interface is ?1? when the 8051 is sleeping with control of the flash or can optionally be configured to follow nfrd (see programmable flash chip select on page 196). the external flash rom interface timing for the high-performance 8051 core is shown below in figure 18. the preliminary flash rom address read-access times are shown in table 84 . ( note: these specifications are subject to change ) table 84 - flash address access times 8051 clock (mhz) flash address access time (ns) 24 65 16 115 12 165 c1 c2 c3 c4 cycle clock fale nfrd fad[7:0] fa[8:18] a0 ? a7 out address instruction in address a8 ? a18 out t address access figure 18 - 8051 program read flash rom interface timing
153 8051 control registers special function registers (sfrs) the high-performance 8051 includes sfrs to support the extended interrupt unit and timer 2 (table 85 ). the high-performance 8051 does not support the misz register. table 85 - 8051 control registers starting address fix bit registers register reset value register name d7 d6 d5 d4 d3 d2 d1 d0 sp 81 h 7 h dplo 82 h dpho 83 h dpl1 (1) 84 h dph1 (1) 85 h dps (1) 86 h 0 0 0 0 0 0 0 sel pcon 87 h smo d0 - 1 1 gf1 gf0 sto p idle 30 h tcon 88 h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 tmod 89 h gate c/t m1 m0 gate c/t m1 m0 tl0 8a h tl1 8b h th0 8c h th1 8d h ckcon (1,3) 8e h - - t2m t1m t0m md2 md1 md0 1 h exif (1) 91 h ie5 ie4 ie3 ie2 1 0 0 0 8 h mpage (1,2) 92 h 00 h scon* 98 h sm0_ 0 sm1 _0 sm2 _0 ren _0 tb8_ 0 rb8 _0 ti_0 ri_0 sbuf 99 h ie a8 h ea es1 et2 es0 et1 ex1 et0 ex0 ip* b8 h 1 ps1 pt2 ps0 pt1 px1 pt0 px0 t2con c8 h tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/ rl2 rcap2l ca h rcap2h cb h tl2 cc h th2 cd h psw d0 h cy ac f0 rs1 rs0 ov f1 p eicon (1) d8 h smo d1 1 epfi pfi wdti 0 0 0 40 h acc e0 h
154 starting address fix bit registers register reset value register name d7 d6 d5 d4 d3 d2 d1 d0 eie (1) e8 h 1 1 1 ew di ex5 ex4 ex3 ex2 e0 h b f0 h eip (1) f8 h 1 1 1 pw di px5 px4 px3 px2 e0 h (1) not part of standard 8051 architecture. see appendix b. (2) the mpage special function register provides a means of 16-bit addressing without using the data pointer. during movx a, @ri and movx @ri, a instructions, the 8051 places the contents of the mpage register on the upper 8 address bits. the mpage register default is ?00h?. (3) the tm2 bit in the ckcon register is available, but not used, when timer 2 is not implemented (timer =0). *=bit-addressable register memory mapped control registers (mmcrs) mmcr summary the memory mapped control registers are on- chip memory-mapped registers that can be accessed by the 8051 but are external to the 8051 core (table 86 ). the 8051 can access all of the memory mapped control registers. the 8051 mmcr addresses are described in column #4 (8051 addr) in table 86 . some mmcrs can also be accessed through the isa host interface (isaxxh), the mailbox registers interface (mbxxxh), the embedded controller interface (eci base), and the acpi pm1 block interface (pm1). these addresses are described in column #2 (system address) in table 86 . these memory mapped control registers can be accessed by the following types of 8051 instructions. movx a,@dptr movx @dptr,a mov mpage,#7fh movx a,@rx (r0 or r1 only) mov mpage,#7fh movx @rx,a (r0 or r1 only)
155 t able 86 - 8051 on-chip external memory mapped registers register name system address system addr. type 8051 addr. (7f00+) 8051 type power plane vcc1 por vcc2 por zero wait state (8) ref. page# n o t e s reserved - - f0h w vcc1 - - 7 host i/f data reg [kbd data/command write reg.] isa 60h isa 64h w f1h r vcc1 - y 205 1,7 host i/f data reg [kbd data read reg.] isa 60h r f1h w vcc1 - y 205 7 host i/f status reg [kbd status reg.] isa 64h r f2h r/w vcc1 00h y 205 2,7 rtc address 1 r/w - - vcc1 00h - 13 rtc data 1 r/w - - vcc1 - - 13 rtc address 2 r/w - - vcc1 00h - 13 rtc data 2 r/w - - vcc1 - - 13 htimer - - f3h r/w vcc1 00h 177 config reg 0 - - f4h r/w vcc1 00h 163 rtccntrl - - f5h r/w vcc1 80h 293 6 rtcaddrl - - f6h r/w vcc1 00h 294 rtcdatal - - f7h r/w vcc1 00 294 rtcaddrh - - f8h r/w vcc1 00h 294 rtcdatah - - f9h r/w vcc1 00h 294 aux host data reg [kbd data read reg.] isa 60h r fah w vcc1 - y 205 3,7 gatea20 - - fbh r/w vcc1 01h 210 flash config. - - fch r/w vcc1 00h - - 193 17 pcobf - - fdh r/w vcc1 00h 206 setga20l - - feh w vcc1 - 210 rstga20l - - ffh w vcc1 - 210 interrupt 0 source register - - 00h r/wc vcc1 00h 168 interrupt 0 mask register - - 01h r/w vcc1 00h 170
156 register name system address system addr. type 8051 addr. (7f00+) 8051 type power plane vcc1 por vcc2 por zero wait state (8) ref. page# n o t e s interrupt 1 source register - - 02h r/wc vcc1 00h 170 interrupt 1 mask register - - 03h r/w vcc1 00h 171 keyboard scan out - - 04h w vcc1 20h 215 keyboard scan in - - 04h r vcc1 - 215 - - - 05h - - - - - - - device rev register - - 06h r vcc1 00h 162 device id register (smsc bondout) - - 07h r vcc1 0bh 163 device id register (alt bondout) - - 07h r vcc1 0ah 163 system-to- 8051 mailbox register 0 mbx 82h r/w 08h rc vcc1 00 y 248 4 8051-to- system mailbox register 1 mbx 83h rc 09h r/w vcc1 00 y 249 5 mailbox register [2-f] mbx 84h-91h r/w 0a-17h r/w vcc1 00h y 244 gpio direction register a - - 18h r/w vcc1 00h 262 gpio output register a - - 19h r/w vcc1 00h 262 gpio input register a - - 1ah r vcc1 - 262 gpio direction register b - - 1bh r/w vcc1 02h 263 gpio output register b - - 1ch r/w vcc1 00h 263 gpio input register b - - 1dh r vcc1 - 263
157 register name system address system addr. type 8051 addr. (7f00+) 8051 type power plane vcc1 por vcc2 por zero wait state (8) ref. page# n o t e s gpio direction register c - - 1eh r/w vcc1 00h 264 gpio output register c - - 1fh r/w vcc1 00h 264 gpio input register c - - 20h r vcc1 - 264 led register - - 21h r/w vcc1 00h 249 out register d - - 22h r/w vcc1 00h 265 out register e - - 23h r/w vcc1 00h 265 in register f - - 24h r vcc1 - 265 pwm0 register mbx 92h r/w 25h r/w vcc1 00h y 252 pwm1 register mbx 93h r/w 26h r/w vcc1 00h y 252 kstp_clk - - 27h r/w vcc1 10h 143 fan control register mbx 9d r/w 28h r/w vcc1 30h y 253 kmem - - 29h r/w vcc1 00h 188 wakeup source 1 - - 2ah r/wc vcc1 00h 172 wakeup source 2 - - 2bh r/wc vcc1 00h 173 wakeup mask 1 - - 2ch r/w vcc1 00h 175 wakeup mask 2 - - 2dh r/w vcc1 00h 175 - - - 2eh - - - - - - - kstp_clk_2 - - 2fh r/w vcc1 00h - - 142 - multiplexing 3 register - - 30h r/w vcc1 00h 272 access.bus control reg - - 31h w vcc1 00h 239 access.bus status reg - - 31h r vcc1 81h 239 access.bus own address reg - - 32h r/w vcc1 00h 239 access.bus data reg - - 33h r/w vcc1 00h 240 access.bus clock - - 34h r/w vcc1 00h 240 - - - 35h - - - -
158 register name system address system addr. type 8051 addr. (7f00+) 8051 type power plane vcc1 por vcc2 por zero wait state (8) ref. page# n o t e s - - - 36h - - - - wdt control/status - - 37h r/w vcc1 00h 184 wdt timer - - 38h r/w vcc1 ffh 184 - - - 39h - - - - - - - pp status reg - 3ah r/w vcc2 00h 257 9 pp control reg - - 3bh r/w vcc2 00h 258 pp data reg - - 3ch r/w vcc2 00h 258 multiplexing 1 register - - 3dh r/w vcc1 00h 266 output enable register 3eh r/w vcc1 see note see note 164 11 disable register - - 3fh r/w vcc1 00h 162 multiplexing 2 register - - 40h r/w vcc1 00h 270 ps/2 port1 control/ ps/2 chan a tx/rx - - 41h r/w vcc2 - 00h 227 7 ps/2 port1 status/ ps/2 chan a control - - 42h r r/w vcc2 - 40h 229 7 ps/2 port1 error/ ps/2 chan a status - - 43h r vcc2 - 00h 231 7 ps/2 port1 transmit - - 44h w vcc2 - 00h 232 ps/2 port1 receive/ ps/2 chan b tx/rx - - 45h r r/w vcc2 - 00h 232 7 ps/2 chan b control - - 46h r/w vcc2 - 40h 220 ps/2 chan b status - - 47h r vcc2 - 00h 222 ps/2_ status_2 - - 48h r vcc2 - 00h - 224
159 register name system address system addr. type 8051 addr. (7f00+) 8051 type power plane vcc1 por vcc2 por zero wait state (8) ref. page# n o t e s ps/2 port2 control/ ps/2 chan c tx/rx - - 49h r/w vcc2 - 00h 227 7 ps/2 port2 status/ ps/2 chan c control - - 4ah r r/w vcc2 - 40h 229 7 ps/2 port2 error/ ps/2 chan c status - - 4bh r vcc2 - 00h 231 7 ps/2 port2 transmit - - 4ch w vcc2 - 00h 232 ps/2 port2 receive/ ps/2 chan d tx/rx - - 4dh r r/w vcc2 - 00h 232 7 ps/2 chan d control - - 4eh r/w vcc2 - 40h - 220 ps/2 chan d status 4fh r vcc2 - 00h 222 - - - 50h- 51h - - - - - - 8051_sirq - - 52h r/w vcc1 00h - - 181 ec_data eci base r/w 53h r/w vcc1 00h y 84 12 ec_ command eci base+4 w 53h r/w vcc1 00h y 84 12 ec_status eci base+4 r 54h r/w vcc1 00h y 84 12 - - - 55h - - - - - - - - - - 56h - - - - - - - edge select 4a 57h r/w vcc1 00h 178 edge select 4b 58h r/w vcc1 00h 178 wake up src 4 59h r/wc vcc1 00h 173 wake up mask 4 5ah r/w vcc1 00h 176 - - - 5bh - - - - - - -
160 register name system address system addr. type 8051 addr. (7f00+) 8051 type power plane vcc1 por vcc2 por zero wait state (8) ref. page# n o t e s edge select 5a 5ch r/w vcc1 00h 178 edge select 5b 5dh r/w vcc1 00h 179 wake up src 5 5eh r/wc vcc1 00h 174 wake up mask 5 5fh r/w vcc1 00h 176 - - - 60h - - - - - - - edge select 6a 61h r/w vcc1 00h 179 edge select 6b 62h r/w vcc1 00h 180 wake up src 6 63h r/wc vcc1 00h 174 - - - 64h- 65h - - - - wake up mask 6 66h r/w vcc1 00h 177 access.bus 2 control reg - - 67h w vcc1 00h 241 access.bus 2 status reg - - 67h r vcc1 81h 241 access.bus 2 own address reg - - 68h r/w vcc1 00h 242 access.bus 2 data reg - - 69h r/w vcc1 00h 242 access.bus 2 clock - - 6ah r/w vcc1 00h 242 - - - 6bh ? 6fh - - - - - - - mailbox registers[10- 1f] mbx a0-af r/w 70h- 7fh r/w vcc1 00 y 244 pm1_sts2 pm1+1 r/wc 80h r/w vcc1 00 y 279 pm1_en2 pm1+3 r/w 81h r vcc1 00 y 280 pm1_cntrl2 pm1+5 r/w 82h r vcc1 00 y 281 8051_pm_ sts - - 83h r/w vcc1 00 - - 282 - pwrgd_int - - 84h r/wc vcc1 00 - - 180 15
161 register name system address system addr. type 8051 addr. (7f00+) 8051 type power plane vcc1 por vcc2 por zero wait state (8) ref. page# n o t e s - - - 85h- 8dh - - - - - - - test register - - 8eh- 8fh - - - - - - - - - - 90h- efh - - - - - - - 256 bytes of ram - - 7e00- 7effh r/w vcc1 146 notes: 1. although the input and output data registers are physically separate, they share address 7ff1. 2. the 8051 cpu cannot write to some bits of the status register. 3. writing to the auxiliary output data register, loads the output data register and can set the auxobf1 output if enabled. this does not set the pcobf output. 4. interrupt is cleared when read by the 8051. 5. interrupt is cleared when read by the host. 6. see rtc control register definition. 7. these addresses are shared between the ps/2 devil logic and the smsc ps/2 hardware channels a ? d (see ps/2 device interface section on page 221). 8. when accessed for a read or write by the system the registers marked with a ?y? will drive the zero wait state pin active. 9. bit 0 is the only writable or resetable bit in this register. 10. when ireset_out is cleared (written from ?1? to?0?) 8051stp_clk bit d0 as well as hmem bits d1 and d0 are all set to ?1?. 11. vcc1 por = 00000x10b, vcc2 por = 00000x1 x b where x is not affected by vcc2 por, but is left at the current value. 12. these registers have the same structure as the keyboard interface registers. 13. the isa rtc registers are relocatoable and accessed by the 8051 through mmcrs 0x7ff5 ? 0x7ff9. 14. see section general purpose i/o (gpio) on page 265. 15. see power fail irq on page 184. 16. see flash configuration register on page 197. 17. smsc ps/2 status_2 registers section on page 229.
162 8051 configuration/control memory mapped registers disable register table 87 - disable register host address 8051 address power plane default - 0x7f3f vcc1 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 type r/w r/w r/w r/w r/w r/w r/w r/w bit name parallel port 1 = enable 0 = disable serial port 1 = enable 0 = disable ir port 1 = enable 0 = disable floppy port 1 = enable 0 = disable ud 1 system flash interface 1=enable 0= d isable re- ser- ved force wrtprt 2 note 1 the ud bits are user-defined. ud bits are maintained by 8051 software, only. note 2 see section fdc force write protection page 84 for a description of th e force wrtprt bit function. device rev register by reading this register, 8051 firmware can confirm the device revision that it is running on. table 88 - device rev register host n/a 8051 0x7f06 (r) power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 8051 r r r r r r r r r bit description current revision 1 this register is hardwired.
163 device id register by reading this register, 8051 firmware can determine which device it is running on. table 89 - device id register host n/a 8051 0x7f07 (r) power vcc1 default 0x0a d7 d6 d5 d4 d3 d2 d1 d0 8051 r r r r r r r r r bit description 0 0 0 0 0 1 1 1 configuration register table 90 - configuration register 0 host n/a 8051 0x7ff4 power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 auxh 0 obfen ps2_sel mmc pcobfen saen sleepflag auxh aux in hardware; when high, auxobf of the status register is set in hardware by a write to 7ffah. when low, auxobf of the status register is a user defined bit (ud) and r/w. obfen when set pcobf is gated onto kirq and auxobf1 is gated onto mirq. when low, kirq and mirq are driven low. software should not change this bit when obf of the status register is equal to 1. mmc memory map control bit : when mmc=0, a 256 byte scratch ram area at 7d00h is available to the 8051. when mmc=1 the scratch ram at 7d00h-7dffh becomes scratch rom at 00h--ffh. pcobfen when high, pcobf reflects whatever value was written to the pcobf firmware latch assigned to 7ffdh. when low, pcobf reflects the status of writes to 7ff1h (the output data register).
164 ps2_sel if ps2_sel=0 (default) then the ps2 device interface logic (devil) is enabled and if ps2_sel=1 then the smsc ps2 interface (sps2) is enabled. the following table illustrates this: ps2_sel internal active ps/2 logic block 0 ps2 device interface logic (devil) 1 smsc ps2 interface logic (sps2) saen software-assist enable. when set to ?1? saen allows control of the gatea20 signal via firmware. if saen is reset to ?0?, gatea20 corresponds to either the last host-initiated control of gatea20 or the firmware write to 7ffeh or 7fffh. sleepflag if sleepflag=?0? when pcon bit-0 is set, the 8051 enters ?idle? mode, whereas if sleepflag=?1? when pcon bit 0 is set the 8051enters ?sleep? mode. this bit is cleared by the occurrence of any wake-up events and on vcc1 por. output enable register table 91 - output enable register host n/a 8051 0x7f3e power vcc1 default 00000x10b on vcc1 por 00000x1xb on vcc2 por output enable register vcc1 por = 0x00000x10, vcc2 por = 00000x1 x b where x means the bit holds its setting preceding vcc2 por. d7-d4 d3 d2 d1 d0 8051 ar r/w r/w r r/w r/w reserved 0 ireset_ ovrd power_good ireset_out 32khz output ar= access rights ireset_out when powergood=1, ireset_out is controlled by the 8051. when powergood=0, ireset_out is forced high (within 100nsec) and latched. the nreset_out pin is not driven until vcc2 is applied. ireset_out cannot be cleared by the 8051 until powergood=1.
165 power_good the power_good bit d2 reflects the state of the FDC37N972 vcc2 power good pin pwrgd. the power_good bit is read-only. ireset_ovrd ireset override - when cleared the ireset_out bit functions as described above. when set, ireset_out is given direct control over the internal reset and nreset_out pins without requiring the stop_clk counter or affecting the 8051stp_clk bit or the hmem register. in the override mode, setting ireset_out drives nreset_out low and clearing ireset_out drives nreset_out high. the reset_out override function allows the 8051 to take the rest of the FDC37N972 chip (sio) out of reset without giving up control (i.e., without stopping its clock and giving the flash interface to the host). on the current FDC37N972, nreset_out is driven high by this sequence of events. sets stp_cnt to a non-zero value clears ireset_out bit, causing 8051stp_clk bit 0 to get set hmem[7:0] to get set to 0x07 and stop counter to start decrementing when stp_cnt reaches 0 the nreset_out pin deasserts (goes high) at which point the 8051?s clock stops and the host owns the flash interface. the above sequence provides a means for the 8051 to directly control the state of the super i/o block?s internal reset. the FDC37N972 provides a means for the 8051 to drive low or toggle the chip?s internal reset without stopping the 8051 clock or giving the flash interface to the host. 32khz output the 32khz output bit d0 controls the FDC37N972 32khz output clock pin 32khz_out. when 32khz output is ?0?, the 32khz output clock is disabled and the 32khz_out pin is driven low. when 32khz output is ?1?, the 32khz output clock is enabled. the 32khz output bit is r/w and disabled by default following vcc1 por. 8051 interrupts 8051 interrupt architechture features the eleven 8051 core interrupts are shown described in table 92 - 8051 interrupts. the 8051 has the following run time sources: int0, int1, int2, int3 and int4. the interrupt sources of int5_n create 8051 wakeup events which are used to monitor and altar the power management state. there are three type of source triggers for wakeup event: nonprogrammable (fixed edge), selectable edge (se), either edge (ee). the 8051 core has three interrupt priority levels: pfi, high and low. the pfi interrupt, if enabled, has priority over all other interrupts.
166 8051 internal parallel interrupts int0 pol tf0 pol int1 pol ri + ti pol tf2 pol reserved reserved tf1 pol 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 wk_ee3 stat wk_ee2 stat wk_ee4 stat accbus2 stat ps2_a/ps2 p1 stat ps2_b/ps2 p2 stat ps2_c stat ps2_d stat any wup_mk sys-mbox_mk accbus1_mk ec_obf_mk ec_ibf_mk kbd scan_mk ibf_mk gpio3_mk 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 any wup stat sys-mbox sta accbus1 sta ec_obf stat ec_ibf stat kbd scan stat ibf stat gpio3 stat int0 mask (0x7f01) int0 src (0x7f00) interrupt polarity sfr interrupt enable sfr int0_en tf0_en int1_en ri + ti_en tf2_en reserved reserved tf1_en int1 mask (0x7f03) int1 src (0x7f02) 5/20/98 8051 interrupts note : wk_ee[2:4] are found at wake up register 2 and int0 register. grp2 int2 int3_n int4 0 1 2 int2 int3 int4 int5_n 3 external interrupt enable sfr pfi power-fail event eicon sfr grp1 grp1 in2 in1 in0 0 1 2 3 4 5 6 7 ngpwkup stat wk_anykey st htimer stat wk_ee2 stat wk_ee4 stat uart_ri1 stat reserved wk_ee3 stat rtc_alrm mk wk_ee1 mk ir_rx mk ab_dat 1 mk pm1_sts_2 mk pm1_en 2 mk pm1_ctl 2 mk ab_dat 2 mk 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 rtc_alrm sta wk_ee1 stat ir_rx stat ab_dat 1 sta pm1_sts_2 sta pm1_en 2 sta pm1_ctl 2 sta ab_dat2 sta wake up src 2 (0x7f2b) wake up msk 2 (0x7f2d) wake up src 1 (0x7f2a) wake up msk 1 (0x7f2c) ngpwkup mk wkanykey mk htimer_mk wk_ee2_mk wk_ee4_mk uart_ri1_mk reserved wk_ee3_mk 0 1 2 3 4 5 6 7 in2 in1 in0 in3 in7 pgi 0 pwrgd_int (0x7f84) 0 1 2 3 4 5 6 7 wk_ee3 msk wk_ee2 msk wk_ee4 msk accbus2 msk ps2_a/ps2 p1 msk ps2_b/ps2 p2 msk ps2_c msk ps2_d msk figure 19 - 8051 interrupts
167 0 1 2 3 4 5 6 7 wk_se00_mk 0 wk_se01_mk 1 wk_se02_mk 2 wk_se03_mk 3 wk_se04_mk 4 wk_se05_mk wk_se06_mk 6 wk_se07_mk 7 wake up src 4 (0x____) wake up msk 4 (0x____) 5 edge select 4 (0x____) wk_se00_src wk_se01_src wk_se02_src wk_se03_src wk_se04_src wk_se05_src wk_se06_src wk_se07_src wk_se00_sel wk_se01_sel wk_se02_sel wk_se03_sel wk_se04_sel wk_se05_sel wk_se06_sel wk_se07_sel 0 1 2 3 4 5 6 7 wk_se10_mk 0 wk_se11_mk 1 wk_se12_mk 2 wk_se13_mk 3 wk_se14_mk 4 wk_se15_mk wk_se16_mk 6 wk_se17_mk 7 wake up src 5 (0x____) wake up msk 5 (0x____) 5 edge select 5 (0x____) wk_se10_src wk_se11_src wk_se12_src wk_se13_src wk_se14_src wk_se15_src wk_se16_src wk_se17_src wk_se10_sel wk_se11_sel wk_se12_sel wk_se13_sel wk_se14_sel wk_se15_sel wk_se16_sel wk_se17_sel 0 1 2 3 4 5 6 7 wk_se20_mk 0 wk_se21_mk 1 wk_se22_mk 2 wk_se23_mk 3 wk_se24_mk 4 wk_se25_mk wk_se26_mk 6 wk_se27_mk 7 wake up src 6 (0x____) wake up msk 6 (0x____) 5 edge select 6 (0x____) wk_se20_src wk_se21_src wk_se22_src wk_se23_src wk_se24_src wk_se25_src wk_se26_src wk_se27_src wk_se20_sel wk_se21_sel wk_se22_sel wk_se23_sel wk_se24_sel wk_se25_sel wk_se26_sel wk_se27_sel 0,1 2,3 4,5 6,7 0,1 2,3 4,5 6,7 0,1 2,3 4,5 6,7 0,1 2,3 4,5 6,7 0,1 2,3 4,5 6,7 0,1 2,3 4,5 6,7 in4 in5 gpio0 gpio1 gpio2 in6 gpio7 gpio4 gpio5 gpio6 gpio8 gpio9 gpio10 gpio11 gpio12 gpio13 gpio14 gpio15 gpio16 gpio17 gpio19 gpio20 gpio21 gpio18 int2 int3 int4 grp2 figure 20 - extended interrupts & wake events note : wake events apply per pin and are available to all functions of that pin. for example, if the irrx function is selected as an alternate function of the gpio8 pin (misc7 = 1), the wk_se12 event can be used for ir wake- up. see section 8051 system power management on page 198.
168 table 92 - 8051 interrupts inter- rupt description natural priority interrupt vector flag enable priority control pfi power fail interrupt 0 0x33 eicon.4 eicon.5 n/a int0_n external interrupt 0 1 0x03 tcon.1 ie.0 ip.0 tf0 timer 0 interrupt 2 0x0b tcon.5 ie.1 ip.1 int1_n external interrupt 1 3 0x13 tcon.3 ie.2 ip.2 tf1 timer 1 interrupt 4 0x1b tcon.7 ie.3 ip.3 ti_0 or ri_0 serial port 0 transmit or receive 5 0x23 scon0.0 (ri_0), scon0.1 (ri_0) ie.4 ip.4 tf2 or exf2 timer 2 interrupt 6 0x2b t2con.7 (tf2), t2con.6 (exf2) ie.5 ip.5 reserved 7 0x3b reserved ie.6 ip.6 int2 external interrupt 2 8 0x43 exif.4 eie.0 eip.0 int3_n (1) external interrupt 3 9 0x4b exif.5 eie.1 eip.1 int4 external interrupt 4 10 0x53 exif.6 eie.2 eip.2 int5_n external interrupt 5 11 0x5b exif.7 eie.3 eip.3 reserved 12 0x63 eicon.3 eie.4 eip.4 note: the int5_n interrupt is used to restart the 8051 from sleep mode. this interrupt includes the interrupt wake up sources from grp1 and grp2 on figure 19 and figure 20 . 8051 int0 source register the eight interrupts in the int0 source register (table 93 ) are logically ?or?ed to drive the 8051 external interrupt 0 input, int0_n (figure 19). when any bit in the int0 source register is ?1?, an interrupt has occurred and, assuming the interrupt is enabled, the 8051 int0_n input is asserted. the bits in the int0 source register are cleared by a writing a ?1? to the bit. table 93 - 8051 int0 source register host address n/a 8051 address 0x7f00 power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 type r/wc r/wc r/wc r/wc r/wc r/wc r/wc r/wc bit name ps2_d ps2_c ps2_b/ ps2 p2 ps2_a/ ps2 p1 access bus 2 wk_ee4 wk_ee2 wk_ee3
169 smsc ps/2 c & d interrupts ? d[7:6] int0 source register bit d7 is the smsc ps/2 channel d interrupt; int0 source register bit d6 is the smsc ps/2 channel c interrupt. these interrupts are active when the ps2_sel control bit d4 in configuration register 0 (0x7ff4) is ?1.? when the smsc ps/2 channels are active the ps2_d interrupt is associated with the ps2clk and ps2dat alternate functions of the gpio20 and gpio21 pins; ps2_c is associated with the imclk and imdata pins. dual-mode smsc/devil interrupts ? d[5:4] int0 source register bits d5 and d4 are multiplexed between the smsc ps/2 channels a and b and the devil logic ports p1 and p2. when the ps2_sel control bit d4 in configuration register 0 (0x7ff4) is ?1,? the smsc ps/2 interrupt channels a and b are selected; when ps2_sel = ?0,? the devil logic ports p1 and p2 are selected. when the smsc ps/2 channels are active the ps2_b interrupt is associated with the kclk and kdat pins; ps2_a is associated with the emclk and emdata pins. access bus 2 interrupt ? d3 ?1? indicates an access.bus 2 interrupt is active. wk_ee[4:2] access bus 2 wake events can be generated. ab_dat access bus 2 bit in wake sources (register 1.) 8051 int0 mask register the eight interrupts in the int0 source register (table 93 ) are enabled by bits of the same name in the int0 mask register (table 94 ). when any bit in the int0 mask register is ?0?, the interrupt is enabled. when any bit in the int0 mask register is ?1, the interrupt is masked. when masked interrupts are asserted, the interrupt will be visible in the interrupt source register but will not assert an interrupt to the 8051. the bits in the int0 mask register are read/write. the int0 interrupts are enabled by default.
170 8051 int0 mask register table 94 - 8051 int0 mask register host address n/a 8051 address 0x7f01 power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 type r/w r/w r/w r/w r/w r/w r/w r/w bit name ps2_d ps2_c ps2_b/ ps2 p2 ps2_a/ ps2 p1 access bus 2 wk_ee4 wk_ee2 wk_ee3 8051 int1 source register the eight interrupts in the int1 source register (table 95 ) are logically ?or?ed to drive the 8051 external interrupt 1 input, int1_n (figure 19). when any bit in the int1 source register is ?1?, an interrupt has occurred and, assuming the interrupt is enabled, the 8051 int1_n input is asserted. bits d0 and d2 ? d6 in the int1 source register are cleared by a writing a ?1? to the bit. table 95 - 8051 int1 source register host address n/a 8051 address 0x7f02 power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 type r r/wc r/wc r/wc r/wc r/wc r r/wc bit name ibf 1 kbd scan ec_ibf 2 ec_obf 3 gpio3 access bus 1 sys-mbox 4 any wup
171 access bus 1 [d2] when access bus 1 bit is equal to 1 an access bus irq is active. ibf [d7] ibf interrupt bit d7 is set when the host writes to the kbd data/command write register and is cleared when the 8051 reads from that register. ec_ibf [d5] ec_ibf interrupt bit d5 is set when the host writes to the ec command or data port (see ibf bit ? d1 on page 88). ec_obf [d4] ec_obf interrupt bit d4 is asserted when the obf bit in the ec status register has been cleared (see obf bit ? d0 on page 88). sys-mbox [d1] sys-mbox interrupt bit d1 is set when the host writes to mailbox register 0. the bit is cleared when mailbox register 0 is read (see the system/8051 interface registers on page 252). 8051 int1 mask register the eight interrupts in the int1 source register (table 95 ) are enabled by bits of the same name in the int1 mask register (table 96 ). when any bit in the int1 mask register is ?0?, the interrupt is enabled. when any bit in the int1 mask register is ?1?, the interrupt is masked. when masked interrupts are asserted, the interrupt will be visible in the interrupt source register but will not assert an interrupt to the 8051. the bits in the int1 mask register are read/write. the int1 interrupts are enabled by default. 8051 int1 mask register table 96 - 8051 int1 mask register host address n/a 8051 address 0x7f03 power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 type r/w r/w r/w r/w r/w r/w r/w r/w bit name ibf kbd scan ec_ibf ec_obf gpio3 access bus 1 sys-mbox any wup
172 8051 wakeup source registers table 97 - wakeup source register 1 host address n/a 8051 address 0x7f2a power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 r/w r/wc r/wc r/wc r/wc r/wc r/wc r/wc r/wc bit name and descrip- tion 1= pm1 ctl 2 1= pm1 en 2 1= pm1 sts 2 1 = ab_dat access. bus interrupt asserted 1 = ab_dat access. bus 2 interrupt asserted 1 = irrx (note 3) 1 = wk_ ee1 change d (note 1) 1 = rtc_ alrm asserted (note 2) res = reserved. read returns 0, writes are ignored. note 1: input is going from low to high or from high to low (read the gpio register to find out the value of pin) ab_dat1 and ab_dat2 -- when access.bus=1, a start condition or other event was detected on the access.bus bus. when access.bus 2=1, a start condition or other event was detected on the access.bus 2 bus pm1_sts2, pm1 en2, pm1ctl2 interrupts: these are set when the corresponding pm1 register has been written by the host. note 2: the rtc_alrm wake-up is an internally generated low-to-high edge, produced when the rtc time updates to match the time of day (tod) alarm setting. this edge will set bit d0 of wake- up source 1 register. bit d0 will remain set and will only be reset on a read of wake-up source 1 register. if the wake-up source register is read before the clock has updated (i.e., rtc still equals the tod alarm) bit d0 is reset and stays reset until the next occurrence of a rtc_alrm wake-up event. note 3: wake event is asserted when only when both v cc2 is active and irrx input changes from high to low. note 4: the interrupt source bits in this register are cleared by a writing a ?1? to the bit.
173 table 98 - wakeup source register 2 host address n/a 8051 address 0x7f2b power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 r/w r r/wc r/wc r/wc r/wc r/wc r/wc r/wc bit name and des- cription res 1 = uart _ri1 assert ed 1= wk_ ee4 1 = wk_ ee2 transiti on (both edges) 1 = wk_ ee3 transiti on (both edges) 1 = htim er timeout s 1 = wk_ anykey is asserted 1= ngpwk up is asserted htimer interrupt when htimer=1, the hibernation timer counted down to zero. note 1: anykey wake-up (wk_anyke? -- when unmasked, the wk_anykey will wake the 8051 from the ?sleep? state when any of the keyboard scan in (ksi) pins goes low. the boolean equation below defines the wk_anykey function. wk_anykey = !(ksi0 & ksi1 & ksi2 & ksi3 & ksi4 & ksi5 & ksi6 & ksi7) note: the interrupt source bits in this register are cleared by a writing a ?1? to the bit. table 99 - wakeup source register 4 host address n/a 8051 address 0x7f59 power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 r/w r/wc r/wc r/wc r/wc r/wc r/wc r/wc r/wc bit name and des- cription 1 = wk_ se07 assert ed 1 = wk_ se06 assert ed 1 = wk_ se05 assert ed 1 = wk_ se04 assert ed 1 = wk_ se03 assert ed 1 = wk_ se02 assert ed 1 = wk_ se01 assert ed 1 = wk_ se00 assert ed note : the bits in this register are cleared on a write of ?1? to the corresponding bit.
174 table 100 - wakeup source register 5 host address n/a 8051 address 0x7f5e power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 r/w r/wc r/wc r/wc r/wc r/wc r/wc r/wc r/wc bit name and description 1 = wk_ se17 assert ed 1 = wk_ se16 assert ed 1 = wk_ se15 assert ed 1 = wk_ se14 assert ed 1 = wk_ se13 assert ed 1 = wk_ se12 assert ed 1 = wk_ se11 assert ed 1 = wk_ se10 assert ed note : the bits in this register are cleared on a write of ?1? to the corresponding bit. table 101 - wakeup source register 6 host address n/a 8051 address 0x7f63 power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 r/w r/wc r/wc r/wc r/wc r/wc r/wc r/wc r/wc bit name and description 1 = wk_ se27 assert ed 1 = wk_ se26 assert ed 1 = wk_ se25 assert ed 1 = wk_ se24 assert ed 1 = wk_ se23 assert ed 1 = wk_ se22 assert ed 1 = wk_ se21 assert ed 1 = wk_ se20 assert ed note : the bits in this register are cleared on a write of ?1? to the corresponding bit.
175 table 102 - wakeup mask register 1 host address n/a 8051 address 0x7f2c power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 r/w r/w r/w r/w r/w r/w r/w r/w r/w bit name and description 1 = mask pm1 ctl2 1 = mask pm1 en2 1 = mask pm1 sts2 1 = mask ab_d ata acce ss bus 1 1 = mask ab_d ata acce ss. bus 2 1 = m ask irrx 1=ma sk wk_ ee1 1 = mask rtc_ alarm table 103 - wakeup mask register 2 host address n/a 8051 address 0x7f2d power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 r/w r r/w r/w r/w r/w r/w r/w r/w bit name and description re se rv ed 1=mask uart_ ri1 1=mask wk_ee 4 1 = mask wk_ ee2 1 = mask wk_ ee3 1 = mask htim er 1 = mask wk_ any key 1= mask ngpwk up
176 table 104 - wakeup mask register 4 host address n/a 8051 address 0x7f5a power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 r/w r/w r/w r/w r/w r/w r/w r/w r/w bit name and description 1 = mask wk_ se07 1 = mask wk_ se06 1 = mask wk_ se05 1 = mask wk_ se04 1 = mask wk_ se03 1 = mask wk_ se02 1 = mask wk_ se01 1 = mask wk_ se00 table 105 - wakeup mask register 5 host address n/a 8051 address 0x7f5f power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 r/w r/w r/w r/w r/w r/w r/w r/w r/w bit name and description 1 = mask wk_s e17 1 = mask wk_ se16 1 = mask wk_ se15 1 = mask wk_ se14 1 = mask wk_ se13 1 = mask wk_ se12 1 = mask wk_ se11 1 = mask wk_ se10
177 table 106 - wakeup mask register 6 host address n/a 8051 address 0x7f66 power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - 8051 r/w r/w r/w r/w r/w r/w r/w r/w r/w bit name and description 1 = mask wk_ se27 1 = mask wk_ se26 1 = mask wk_ se25 1 = mask wk_ se24 1 = mask wk_ se23 1 = mask wk_ se22 1 = mask wk_s e21 1 = mask wk_se 20 8051 hibernation timer register table 107 - htimer register host n/a 8051 0x7ff3 power vcc1 default 0x00 hibernation timer - this 8 bit binary count-down timer can be programmed for from 30 seconds to 128 minutes in 30 second increments. when it expires (reaches ?0?), it stops (remains at ?0?) and causes a hardware event that will wake up the 8051. this timer is clocked by the 32 khz clock and is powered by vcc1. writing a non-zero value to this register starts the counter from that value. 8051 edge select registers selectable edge interrupts selectable interrupts se00-se07 are on external int2. selectable interrupts se10-se17 are on external int3. selectable interrupts se20-se27 are on external int4.
178 table 108 - edge select 4a host address n/a 8051 address 0x7f57 power vcc1 default 0x00 d7:6 d5:4 d3:2 d1:0 host type - - - - 8051 r/w r/w r/w r/w bit name and description se03 select se02 select se01 select se00 select table 109 - edge selection edge selection table d7:6 d5:4 d3:2 d1:0 edge high to low 00 edge low to high 01 either edge 10 reserved 11 table 110 - edge select 4b host address n/a 8051address 0x7f58 power vcc1 default 0x00 d7:6 d5:4 d3:2 d1:0 host type - - - - 8051 r/w r/w r/w r/w bit name and description se07 select se06 select se05 select se04 select refer to table 109 - edge selection for the edge selection table table 111 - edge select 5a host address n/a 8051 address 0x7f5c power vcc1 default 0x00
179 d7:6 d5:4 d3:2 d1:0 host type - - - - 8051 r/w r/w r/w r/w bit name and description se13 select se12 select se11 select se10 select refer to table 109 for the edge selection table. table 112 - edge select 5b host address n/a 8051 address 0x7f5d power vcc1 default 0x00 d7:6 d5:4 d3:2 d1:0 host type - - - - 8051 r/w r/w r/w r/w bit name and description se17 select se16 select se15 select se14 select refer to table 109 for the edge selection table. table 113 - edge select 6a host address n/a 8051 address 0x7f61 power vcc1 default 0x00 d7:6 d5:4 d3:2 d1:0 host type - - - - 8051 r/w r/w r/w r/w bit name and description se23 select se22 select se21 select se20 select refer to table 109 for the edge selection table.
180 table 114 - edge select 6b host address n/a 8051 address 0x7f62 power vcc1 default 0x00 d7:6 d5:4 d3:2 d1:0 host type - - - - 8051 r/w r/w r/w r/w bit name and description se27 select se26 select se25 select se24 select refer to table 109 for the edge selection table. power fail irq the pwrgd_int register (table 115 ) contains the power good interrupt (pgi) bit, d0. when pgi = ?1?, the (vcc2) pwrgd input has been deasserted; otherwise, pgi = ?0?. note: pgi is not asserted when pwrgd is asserted. the pgi bit is the source for the high-performance 8051 power fail interrupt (pfi) input ( figure 19 ). the vcc2 power fail detect function is implemented as described in 8051 ring oscillator fail- safe controls on page 147. the pgi bit is readable and is cleared by writing a ?1? to d0 in the pwrgd_int register. table 115 - power good interrupt register (pwrgd_int) host address 8051 address power plane default - 0x7f84 vcc1 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 type r r r r r r r r/wc bit name reserved pgi
181 8051 external serial irq generation the 8051 can assert an interrupt on the serial irq stream to support software-generated sci, smi, or pme events (figure 21). figure 21 note: the 8051 external serial irq is generated and cleared by software. the 8051 external serial irq interface is controlled by the 8051_sirq register (table 116 ). irq mapping logic serial irq 8051_irq 8051_irq select figure 21 - 8051 external serial irq block diagram table 116 - 8051_sirq register host address 8051 address power plane default - 0x7f52 vcc1 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 type r/w r/w r/w r/w r/w r/w r r bit name 8051_irq select 8051_irq enable 8051_irq reserved 8051_irq select four bits that selects which irq is utilized when an interrupt occurs. see table 117 - 8051 irq mapping control bits 8051_irq enable this bit must be set to one in order for an interrupt to occur.
182 8051 irq this bit must set to one in order for the 8051 to assert the mapped interrupt request corresponding to the 8051_irq select bits. the defualt state for a disabled irq is asserted. table 117 - 8051 irq mapping control bits 8051_irq enable 8051_irq select description 0 xxxx disabled 1 0000 no interrupt 1 0001 map to irq1 1 0010 map to irq2 1 0011 map to irq3 1 0100 map to irq4 1 0101 map to irq5 1 0110 map to irq6 1 0111 map to irq7 1 1000 map to irq8 1 1001 map to irq9 1 1010 map to irq10 1 1011 map to irq11 1 1100 map to irq12 1 1101 map to irq13 1 1110 map to irq14 1 1111 map to irq15
183 watch dog timer wdt operation when enabled, the watch dog timer (wdt) circuit will generate a system reset if the user program fails to reload the watchdog timer (wdt) within a specified length of time known as the ?watchdog interval?. the wdt consists of an 8-bit timer (wdt) with a 9-bit prescaler. the prescaler is fed with 32 khz which always runs, even if the 8051 is in sleep state. the 8 bit wdt timer is decremented every (1/32khz) *512 seconds or 16.0 ms. thus, the watchdog interval is programmable between 16ms and 4.08 seconds on 16ms intervals. wdt action if the 8 bit timer (wdt) underflows, a vcc1 por is generated 8051 in idle mode - wdt will be active if enabled. when the wdt timer underflows in idle mode, the 8051 will be reset. it is up to the firmware engineer to design code that uses a timer to generate an interrupt that will exit idle mode and re-initialize the wdt timer and then put the 8051 back into idle mode. 8051 in sleep mode - if enabled, the wdt is active since it is running off of the 32 khz clock. therefore, if the wdt is enabled the 8051 should never remain in the sleep state for more than 4 seconds. wdt activation upon vcc1 por the watch dog timer powers up inactive. the watch dog timer is activated when the wdt enable bit (wdt control bit d1) is set by 8051 firmware. the wdt may be disabled under software control through a specific sequence. software can clear the sdt enable bit by: setting the wle-wdt load enable bit in the wdt control/status register. writing 00h to the wdt timer register (this causes the wdt enable and the wle_wdt load enable bits to each reset to 0). once the wdt has been activated, this sequence must be executed in order to disable watchdog operation via software control. note: since a vcc1 por will reset the wdt enable bit, the wdt must be re-enabled after each occurrence. wdt reset mechanism the watchdog timer (wdt) must be reloaded within periods that are shorter than the programmed watchdog interval; otherwise the wdt will underflow and a vcc1 por will be generated. it is the responsibility of the user program to continually execute sections of code which reload the 8 bit timer (wdt). the wdt is reloaded in two stages in order to prevent erroneous software from reloading the watchdog. first wdt control bit d0 (wle- wdt load enable) must be set. then the wdt may be loaded. when the wdt is loaded wle is automatically reset. wdt can not be loaded when wle is reset. since the wdt timer is a down counter, a reload value of 01h results in the minimum wdt interval (16ms) and a reload value of 0ffh results in the maximum wdt interval (4.08 seconds). loading 00h into the wdt disables the wdt and clears the wdt enable bit. note, the 9 bit prescaler is initialized whenever the wdt timer is loaded.
184 wdt memory mapped registers table 118 - wdt host address n/a 8051 address 0x 7f38 power vcc1 default 0xff d7 d6 d5 d4 d3 d2 d1 d0 8051 r/w r/w r/w r/w r/w r/w r/w r/w r/w system r/w n/a n/a n/a n/a n/a n/a n/a n/a bit def wdt timer wdt timer wdt timer wdt timer wdt timer wdt timer wdt timer wdt timer table 119 - wdt control/status host address n/a 8051 address 0x 7f37 power vcc1 default 0x00 d7-d2 d1 d0 8051 r/w r r/w r/w system r/w n/a n/a n/a bit def reserved wdt enable wle-wdt load enable wle watchdog load enable bit must be set to enable writing to the wdt timer register. this bit is automatically reset when the 8051 writes to the wdt register. if this bit is reset, writes to the wdt register are ignored. wdt enable the wdt enable bit must be set by 8051 firmware to enable or start the watch dog timer. a vcc1 por or the above described software sequence will reset this bit.
185 shared flash interface a 256kb flash device (i.e., 28f004) is recommended to store the program code for the 8051 (keyboard bios+) and the system bios. the flash memory can be accessed from the system in blocks of 64kb or from the 8051 in blocks of 32kb. the procedure to access the flash memory is described in the host flash access section. flash interface diagram access to the flash memory is multiplexed inside of the FDC37N972. the host cpu only has access to the flash when nreset_out is not asserted and the 8051 stp_clk bit-0 is set. please refer to the timing section for details on this interface. figure 22 - flash interface diagram 512k x 8 flash latch ad[7:0] r o m c s i s a b u s addr[17:8] nkbrd nkbwr ale host cpu nce FDC37N972 n
186 system memory map 64k 8051 rom 512k flash rom 0 7ff 64k host interface 64k 8051 external ram 0 8000 ffff 8000 ffff 16x 32k blocks 0 ffff invalid internal registers figure 23 - system flash access map (alt bondout)
187 64k 8051 rom 512k flash rom 0 64k host interface 64k 8051 external ram 0 8000 ffff 8000 ffff 16x 32k blocks 0 ffff internal registers same as 0-7fff figure 24 - system flash access map (smsc bondout) keyboard bios (kmem) the 8051 uses this register to access the flash rom in a 32k window. the 8051 is only barred from accessing the flash when 8051stp_clk bit d0 =1 and nreset_out= high or deasserted. bit d3 is added to the kmem register to accommodate the high-order flash rom address bit fa18 (table 120). the flash rom memory ranges are decoded as shown in table 121 .
188 table 120 - kmem register host index 8051 address power plane default - 0x7f29 vcc1 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 type r r r r r/w r/w r/w r/w bit name reserved a18 a17 a16 a15 kmem 17 16 15 flash memory range 0 0 0 000- 7fff 0 0 1 8000- ffff 0 1 0 10000-17fff 0 1 1 18000-1ffff 1 0 0 20000-27fff 1 0 1 28000-2ffff 1 1 0 30000-37fff 1 1 1 38000-3ffff table 121 - flash rom address encoding kmem register address range select bits d3 d2 d1 d0 decoded flash rom memory range 0 0 0 0 00000 ? 07fff 0 0 0 1 08000 ? 0ffff 0 0 1 0 10000 ? 17fff 0 0 1 1 18000 ? 1ffff 0 1 0 0 20000 ? 27fff 0 1 0 1 28000 ? 2ffff 0 1 1 0 30000 ? 37fff 0 1 1 1 38000 ? 3ffff 1 0 0 0 40000 ? 47fff 1 0 0 1 48000 ? 4ffff 1 0 1 0 50000 ? 57fff 1 0 1 1 58000 ? 5ffff 1 1 0 0 60000 ? 67fff 1 1 0 1 68000 ? 6ffff 1 1 1 0 70000 ? 77fff 1 1 1 1 78000 ? 7ffff
189 system bios (hmem) hmem register host mbx 0x95 8051 n/a power vcc1 default vcc1 por = 0x03 vcc2 por = 0x03 the system uses this register to select a 64k window for access from the 256k flash rom. the host may access the flash when reset_out pin is de-asserted and 8051stp_clk bit d0 = 1. bit d2 is added to the hmem register to accommodate the high-order flash rom address bit fa18 (table 122 ). table 122 - hmem register host index 8051 address power plane default mbx95h - vcc1 0x07 (vcc1 por) 0x07 (vcc2 por) d7 d6 d5 d4 d3 d2 d1 d0 host type r r r r r r/w r/w r/w 8051 type - - - - - - - - bit name reserved a18 a17 a16 host flash access the FDC37N972 has a special shared flash rom interface. the 8051 can be stopped to allow the host cpu to access the flash rom after a special handshake sequence is followed. host initiated flash access to access the flash memory, the 8051 must first be placed into idle mode, and then the 8051 clock must be stopped. host flash reads and writes occur when the nromcs pin is asserted along with nmemrd or nmemwr. the register bit ?8051_stpclk? needs to be set by the host to make the 8051 clock stop. the 8051 clock is only stopped when 8051stp_clk=1 and when nreset_out pin = high. address bits a[15:0] are supplied by sa[15:0], address bits a[17:16] are supplied by configuration register hmem. for flash access, these address lines and bits are qualified (selected) by 8051stp_clk=1, and the nreset_out pin = high (nreset_out is driven by the 8051). the 8051 stp_clk is set to ?1? and hmem is set to 03h (effectively resulting in a[17:16] initializing as "11") whenever the 8051 clears the ireset_out bit from ?1? to ?0?. this allows the system to execute from the upper 64k of the flash memory at boot time. to access the other portions of the flash memory, the system software must first change the values of hmem[1:0] register to control address lines a[17:16]. the access to the flash memory uses nfwr for a write and nfrd for a read.
190 the host, wishing to access flash memory, issues a user- defined command to put the 8051into idle mode. system fully powered up and running. reset_out=low, 8051stp_clk=0. 8051 owns flash interface, running keyboard code. 8051goes into idle mode when done using flash, the host resets 8051stp_clk bit 8051 timer irq ? y n the host sets 8051stp_clk = 1 combined with reset_out = low; this causes 8051 clock to stop. host now owns flash interface. 8051 wakes up from idle mode and starts executing from where it left off. (note) note: in order to leave idle mode the 8051 must receive an interrupt; typically a software timer interupt will be used. figure 25 - dynamic sharing of flash interface between host and 8051
191 table 123 - 8051 stp_clk register host mbx 0x94 8051 n/a power vcc1 default 0x00 d7 d6 d5-d1 d0 idle host_ flash reserved, set to ?0? 0=8051 clock can run 1=8051 clock stop note: when bit d0=1 the 8051?s clock is not stopped unless the nreset_out pin is also de-asserted at which point the host has access to the flash memory. note: only bit d0 is r/w, bits[7:1] are read only. idle : 0 = 8051 not in idle mode 1= 8051 in idle mode host_flash: 0 = host does not have access to flash, in use by 8051 1 = host has access to flash host boot block select the FDC37N972 can optionally support 16k and 64k boot block flash roms and can boot out of the same flash rom address space as the 8051. the 64k host boot bit and the 16k host boot bit, d1 and d0 respectively in the flash configuration register ( table 127 ) determine the host boot block options ( table 124 ). for more information regarding the 64k host boot bit and the 16k host boot bit, see flash configuration register on page 197. the host boot block options described in table 124 apply to host flash addresses, only. table 124 - host boot block option flash configuration register d1 d0 mode description 0 0 normal host flash address bits 18 ? 16 are under control of the hmem register ( default ). 0 1 16k mode host flash address bits 18 ? 14 are forced to ?0?. 1 0 64k mode host flash address bits 18 ? 16 are forced to ?0?. 1 1 undefined do not use.
192 programmable flash chip select the FDC37N972 flash rom chip select output nfcs can be optionally deasserted ?1? when the 8051 is sleeping with control of the flash, or asserted and deasserted according to the flash rom read strobe nfrd. the alt chip select bit d2 in the flash configuration register ( table 127 ) selects the flash rom chip select option. the effects of the alt chip select bit are shown in table 125 . for more information regarding the alt chip select bit, see flash configuration register on page 197. table 125 - flash rom chip select options flash config. register d2 mode description 0 normal nfcs deasserted when 8051 is sleeping with control of the flash ( default ). 1 read nfcs follows nfrd. flash rom write redirection the flash rom write control nfwr can be optionally redirected to an alternate function of the out3 pin to support functions like an i/o port expander. the alt write select bit d3 in the flash configuration register ( table 127 ) selects the flash rom write redirection option. the effects of the alt write select bit are shown in table 126 - flash rom write redirection options . for more information regarding the alt write select bit, see flash configuration register on page 197.
193 table 126 - flash rom write redirection options flash config. register d3 mode description 0 normal the out3 pin is configured as a general purpose output and flash rom ?writes? appear on the nfwr pin ( default ). 1 write redirection the out3 pin is configured as an inverted flash rom ?write? strobe, fwr. note: flash rom ?writes? do not appear on the nfwr pin but appear inverted on the fwr pin. flash configuration register overview the flash configuration register ( table 127 is used to select the various options described in this document.) the fcr is a vcc1 register. the bits in the fcr are r/w and cleared by vcc1 por. detailed descriptions of these bits follow, below. table 127 - flash configuration register host address - 8051 address 0x7ffc power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 type r r r r r/w r/w r/w r/w bit name reserved alt write select alt chip select 64k host boot 1 16k host boot 1 note 1 bits d0 and d1 are cleared by vcc1_por or host writes to the hmem register.
194 alt write select bit, d3 the alt write select bit is used to select flash rom write redirection option shown in table 126 - flash rom write redirection options . see flash rom write redirection, above, for a description of this function. the alt write select bit is also used as the out3 pin alternate function multiplex control ( table 4 ). the 8051 can read and write the alt write select bit. the bit is ?0? by default and is cleared by vcc1_por. alt chip select bit, d2 the alt chip select bit selects the flash rom chip select option shown in table 125 . see programmable flash chip select , above, for a description of this function. the 8051 can read and write the alt chip select bit. the bit is ?0? by default and is cleared by vcc1_por. 64k host boot bit, d1 the 64k host boot bit is used to select the 64k mode host boot block option shown in table 124 . see host boot block select, above, for a description of this function. note : the 16k host boot bit d0 must not be set to a ?1? when the 64k host boot bit is ?1?. the 8051 can read and write the 64k host boot bit. the 64k host boot bit is cleared by vcc1_por or host writes to the hmem register. 16k host boot bit, d0 the 16k host boot bit is used to select the 16k mode host boot block option shown in table 124 . see host boot block select, above, for a description of this function. note : the 64k host boot bit d1 must not be set to a ?1? when the 16k host boot bit is ?1?. the 8051 can read and write the 16k host boot bit. the 16k host boot bit is cleared by vcc1_por or host writes to the hmem register. 8051 system power management the high-performance 8051 core provides support for two further power-saving modes, available when inactive: idle mode, typically entered between keystrokes; and sleep mode, entered upon command from the host. the high performance 8051 is wakeable from sleep mode through a set of external and internal events called wake-up events. the events are listed in table 128 . when exiting the sleep mode, the high performance 8051 will continue executing code from where it left off when put into sleep with no changes to the sfr and pins. the FDC37N972 is fully static and will pickup from where it left off in the event of a wake-up event.
195 idle mode entering idle mode: idle mode is initiated by an instruction that sets the pcon.0 bit (sfr address 87h) in the keyboard. in idle mode, the internal clock signal to the keyboard cpu is gated off, but not to the interrupt timer and serial port functions. the cpu status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator, and all other registers maintain their data. the port pins hold the logical levels they had when idle mode was activated.
196 system fully powered up and running. reset_out=low, 8051stp_clk=0. 8051 owns flash interface, running keyboard code. 8051 now in idle mode, 8051 clock running. the host either issues a user- defined command to put the 8051into idle mode, or the 8051 code determines that the 8051 should enter idle mode. sleepflag = 0 pcon.0 = 1 figure 26 - entering idle mode
197 unmasked 8051 irq ? n 8051 returns to executing from where it left off prior to entering idle mode. (note) 8051 in idle mode, 8051 clock running. note: in order to leave idle mode the 8051 must receive an interrupt, typically a software timer interrupt will be used. y 8051 leaves idle mode, executes irq service routine code and executes an iret when done. figure 27 - exiting idle mode due to irq exiting idle mode there are two ways to terminate idle mode. first, activation of any enabled interrupt will cause the pcon.0 bit to be cleared by hardware. the interrupt will be serviced and, following the reti, the cpu will resume operation by executing the instruction following the one that put the cpu into idle mode. the second way to terminate the idle mode is with a vcc1 por. note that a vcc1 por will clear the registers. the cpu will not resume program execution from where it left off. sleep mode when the cpu enters sleep mode, all internal clocks, including the core clocks, are turned off. if an external crystal is used, the internal oscillator is turned off. ram contents are preserved. sleep mode is initiated by a user defined 8051 command sequence.
198 sleep mode sequence to enter sleep mode, the 8051: turns on the ring oscillator (kstp_clk[4] = 1) switches the clock source (kstp_clk[5] = 0) turns off the clock chip (or the whole system power, vcc2) masks all interrupts except for int5_h sets sleepflag = 1 sets pcon.0 = 1 the ring oscillator will be automatically turned off the 8051 goes into sleep mode. in sleep mode, the fdc, uart and parallel port are powered off if vcc2 is removed, but the rtc and 8051 are in powerdown (sleep) mode. in sleep mode the FDC37N972 consumes less than 20 m a, and all wake-up pins are still active. when the 8051 is in sleep mode, all of the clocks are stopped and the 8051 is waiting for an unmasked wake-up event. when the wake- up event occurs, the ring oscillator is started the 8051 starts executing from where it stopped in the sleep mode sequence. once running, the 8051 can access all of the registers that are on vcc1 and if vcc2 is at 3.3v it can access all of the registers on vcc2. the 8051 running from the ring oscillator (internal) clock source switch to an external clock sourceand then turn off the ring oscillator (internal) clock source.
199 system fully powered up and running. reset_out= low, 8051stp_clk= 0. 8051 owns flash interface, running keyboard code. 8051 now in sleep mode, 8051 clock stopped. the host either issues a user- defined command to put the 8051into sleep mode, or the 8051 code determines that the 8051 should enter sleep mode. sleepflag = 1 pcon.0 = 1 8051 switches its clock source to the ring oscillator. 8051 masks all interrupts except for t5int. ring oscillator first gated off from 8051, then turned off. the 8051 may/may not turn off vcc2 to rest of system. figure 28 - entering sleep mode
200 8051 in sleep mode. rtc, 8051 and other vcc1 driven pins are active unmasked wake-up event ? n y int5_n generated. turn on ring oscillator. sleepflag = 0. once stabilized, the ring oscillator is gated through to the 8051. the 8051 is now running in idle mode and responds immediately to t5int. 8051 returns to executing from where it left off prior to entering sleep mode. 8051 leaves idle mode, executes int5_n service routine (disables int5_n) and executes an iret when done. wake up events rtc alarm, power button, ring indicator, etc. figure 29 - exiting sleep mode
201 wake-up events there are two types of wake-up events that can occur, internal ( table 128 ? internal system wake-up events ) and external ( table 129 ). wake-up events on general purpose pins can be either edge or selectable edges. refer to table table 109 for further description. wake-up events can occur when vcc2 is off. vcc1 must be on for a wake-up event to occur, but the high-performance 8051 can be in sleep mode. table 128 ? internal system wake-up events wake-up events register description rtc_alrm wake up src 1 (0x7f2b) [d0] rtc alarm htimer wake up src 2 (0x7f2b) [d2] hibernation timer pm1_sts2 wake up src 1 (0x7f2a) [d5] pm1 status pm1_en2 wake up src 1 (0x7f2a) [d6] pm1 enable pm1_ctl2 wake up src 1 (0x7f2a) [d7] pm1 control table 129 - external system wake-up events pin wake-up events active edge register description nri uart_ri1 edge, high-to- low wake up src 2 (0x7f2b) [d6] uart ring indicator ab1_data accbus1 leading edge, high-to-low wake up src1 (0x7f2a) [d4] ab_dat access bus1 ab2_data accbus2 leading edge, high-to-low wake up src1 (0x7f2a) [d3] ab_dat access bus2 irrx ir_rx edge, high-to- low wake up src1 (0x7f2b) [d2] ir energy detected on the irrx receive pin ksi[7:0] wk_anykey edge, high-to- low wake up src 2 (0x7f2b) [d1] any keyboard key pressed gpio0/ wk_se02 programmable wake up src 4 (0x7f59) [d2] general purpose pin gpio1 wk_se03 programmable wake up src 4 (0x7f59) [d3] general purpose pin gpio2 wk_se04 programmable wake up src 4 (0x7f59) [d4] general purpose pin gpio3 trigger programmable int src 1 (0x7f02) [d3] general purpose pin gpio4 wk_se07 programmable wake up src 4 (0x7f59) [d7] general purpose pin
202 pin wake-up events active edge register description gpio5 wk_se10 programmable wake up src 5 (0x7f5e) [d0] general purpose pin gpio6 wk_se11 programmable wake up src 5 (0x7f5e) [d1] general purpose pin or fir mode output/ 2 nd receive input gpio7 wk_se06 programmable wake up src 4 (0x7f59) [d6] general purpose pin gpio8 wk_se12 programmable wake up src 5 (0x7f5e) [d2] gpio8 or ir energy detected on the gpio/com-rx receive pin. gpio9 wk_se13 programmable wake up src 5 (0x7f5e) [d3] general purpose pin gpio10 wk_se14 programmable wake up src 5 (0x7f5e) [d4] general purpose pin or fir mode output/ 2 nd receive input gpio11 wk_se15 programmable wake up src5 (0x7f5e) [d5] gpio11 or access.bus 2 serial data gpio12 wk_se16 programmable wake up src5 (0x7f5e) [d6] gpio12 or access.bus 2 clock gpio13 wk_se17 programmable wake up src5 (0x7f5e) [d7] general purpose pin gpio14 wk_se20 programmable wake up src6 (0x7f63) [d0] general purpose pin gpio15 wk_se21 programmable wake up src6 (0x7f63) [d1] general purpose pin gpio16 wk_se22 programmable wake up src6 (0x7f63) [d2] general purpose pin gpio17 wk_se23 programmable wake up src6 (0x7f63) [d3] general purpose pin gpio18 wk_se27 programmable wake up src6 (0x7f63) [d7] gpio18 or dma acknowledge gpio19 wk_se24 programmable wake up src6 (0x7f63) [d4] general purpose pin /dma acknowledge gpio20/ ps2clk/ 8051rx wk_se25 programmable wake up src6 (0x7f63) [d5] general purpose pin /ps2 serial clock 8051 rx input gpio21/ ps2dat/ 8051tx wk_se26 programmable wake up src6 (0x7f63) [d6] general purpose pin /ps2 serial data 8051 tx input in0 wk_ee4 either edge wake up src 2 (0x7f2b) [d5] general purpose wakeup source
203 pin wake-up events active edge register description in1 wk_ee2 either edge wake up src 2 (0x7f2b) [d4] general purpose wakeup source in2 wk_ee3 either edge wake up src 2 (0x7f2b) [d5] general purpose wakeup source in3 ngpwkup either edge wake up src 2 (0x7f2b) [d3] general purpose wakeup source in4 wk_se00 either edge wake up src 4 (0x7f59) [d0] general purpose wakeup source in5 wk_se01 either edge wake up src 4 (0x7f59) [d1] general purpose wakeup source in6 wk_se05 either edge wake up src 4 (0x7f59) [d5] general purpose wakeup source in7 wk_ee1 either edge wake up src1 (0x7f2b) [d1] general purpose wakeup source note: all gpio pins can generate wake events and all alternate functions of gpio primary function pins can generate wake events.
204 keyboard controller 8042 style host interface the FDC37N972 keyboard controller uses a high-performance 8051 microcontroller cpu core to produce a superset of the features provided by the industry-standard 8042 keyboard controller. added features include two high-drive serial interfaces, and additional interrupt sources. the FDC37N972 provides an industry standard 8042-style host interface to the high-performance 8051 to emulate standard 8042 keyboard controller and preserve software backward compatibility with the system bios. the FDC37N972?s keyboard isa interface is functionally compatible with the 8042-style host interface. it consists of the sd[0:7] data bus; the nior, niow and the kbd (keyboard) status register, kbd data/command write register, and kbd data read register. table 130 shows how the interface decodes the control signals. in addition to the above signals, the host interface includes keyboard and mouse irq's. table 130 - keyboard controller isa i/o address map isa address niow nior function (note 1, 2 ) 0x60 0 1 keyboard data write (c/d=0) 1 0 keyboard data read 0x64 0 1 keyboard command write (c/d=1) 1 0 keyboard status read all addresses are qualified by aen. note 1: the keyboard interface can be enabled or disabled through the confi guration registers. note 2: these registers consist of three separate 8 bit registers: kbd status, kbd data/command write and kbd data read. keyboard data write this is an 8 bit write only register. when written, the c/d status bit of the status register is cleared to zero and the ibf bit is set. keyboard data read this is an 8 bit read only register. when read, the pbobf and/or auxobf interrupts are cleared and the obf flag in the status register is cleared.
205 keyboard command write this is an 8 bit write only register. when written, the c/d status bit of the status register is set to one and the ibf bit is set. keyboard status read this is an 8 bit read only register. refer to the description of the status register (7ff2h) for more information. 8051- to- host keyboard communication the 8051 can write to the kbd data read register via address 7ff1h and 7ffah (aux host data register) respectively. a write to either of these addresses auto matically sets bit 0 (obf) in the status register. a write to 7ff1h also sets pcobf. a write to 7ffah also sets auxobf1. see table 132 below. table 131 - host-interface flags 8051 address flag 7ff1h (r/w) pcobf (kirq) output signal goes high 7ffah (w) auxobf1 (mirq) output signal goes high host i/f data register host isa 0x60 8051 0x7ff1 power vcc1 default n/a the input data register and output data register are each 8 bits wide. a write to this 8 bit register by the 8051 will load the keyboard data read buffer, set the obf flag and set the pcobf output if enabled. a read of this register by the 8051 will read the data from the keyboard data or command write buffer and clear the ibf flag. refer to the pcobf and status register descriptions for more information. host i/f command register host isa 0x64 (w) 8051 0x7ff1 power vcc1 default n/a the host cpu sends commands to the keyboard controller by writing command bytes to isa port 0x64. host i/f status register host isa 0x64 (r) 8051 0x7ff2 power vcc1 default n/a
206 the status register is 8 bits wide. shows the contents of the kbd status register. table 132 - kbd status register d7 d6 d5 d4 d3 d2 d1 d0 ud ud auxobf/ud ud c/d ud ibf obf this register is read-only for the host and read/write by the 8051. the 8051 cannot write to bits 0, 1, or 3 of the status register. ud read/writeable by 8051. these bits are user-definable. c/d command data - this bit specifies whether the input data register contains data or a command (?0? = data, ?1? = command). during a host data/command write operation, this bit is set to "1" if sa2 = ?1? or reset to "0" if sa2 = 0. ibf input buffer full - this flag is set to ?1? whenever the host system writes data into the input data register. setting this flag activates the 8051's nibf interrupt if enabled. when the 8051 reads the input data register, this bit is automatically reset and the interrupt is cleared. there is no output pin associated with this internal signal. obf output buffer full - this flag is set to ?1? whenever the 8051 writes into the data registers at 7ff1h or 7ffah. when the host system reads the output data register, this bit is automatically reset. auxobf auxiliary output buffer full - this flag is set to ?1? whenever the 8051 writes into the data registers at 7ffah. this flag is reset to ?0? whenever the 8051 writes into the data registers at 7ff1h. pcobf host n/a 8051 0x7ffd power vcc1 default 0x00 refer to the pcobf description for information on this register. this is a ?1? bit register (bits 1- 7=0 on read) host-to 8051 keyboard communication the host system can send both com mands and data to the kbd data/command write regis ter. the cpu differentiates between commands and data by reading the value of bit 3 of the status register. when bit 3 is "1", the cpu interprets the regis ter contents as a command. when bit 3 is "0", the cpu interprets the register contents as data. during a host write operation, bit 3 is set to "1" if sa2 = 1 or reset to "0" if sa2 = 0. pcobf description (the following description assumes that obfen = 1 in configuration register 0); pcobf is gated onto kirq. the kirq signal is a sys tem interrupt which signifies that the 8051 has written to the kbd data read register via address 7ff1h. on power-up, pcobf is reset to 0. pcobf will normally reflect the status of writes to 7ff1h, if pcobfen (bit 2 of configuration register ?0?) = ?0?. (kirq is normally selected as irq1 for keyboard
207 support.) pcobf is cleared by hardware on a read of the host data register. additional flexibility has been added which allows firmware to directly control the pcobf output signal, independent of data transfers to the host-interface data output register. this feature allows the FDC37N972 to be operated via the host "polled" mode. this firmware control is active when pcobfen = 1 and firmware can then bring pcobf high by writing a "1" to the lsb of the 1 bit data register, pcobf, allocated at 7ffdh. the firmware must also clear this bit by writing a "0" to the lsb of the 1 bit data register at 7ffdh. the pcobf register is also readable; bits 1-7 will return a "0" on the read back. the value read back on bit 0 of the register always reflects the present value of the pcobf output. if pcobfen = 1, then this value reflects the output of the firmware latch at 7ffdh. if pcobfen = 0, then the value read back reflects the in-process status of write cycles to 7ff1h (i.e., if the value read back is high, the host interface output data register has just been written to). if obfen=0, then kirq is driven inactive (low). auxobf1 description (the following description assumes that obfen = 1 in configuration register 0); this bit is multiplexed onto mirq. the auxobf1/mirq signal is a sys tem interrupt wh ich signifies that the 8051 has written to the output data register via address 7ffah. on power-up, after vcc1 por, auxobf1 is reset to 0. auxobf1 will normally reflects the status of writes to 7ffah. (mirq is normally selected as irq12 for mouse support.) auxobf1 is cleared by hardware on a read of the host data register. if obfen=0, then kirq is driven inactive (low). host i/f status register bits write to register auxobf (d5) obf (d0) obfen=0 obfen=1 7ff1 0 1 kirq=0 kirq=1 7ffa 1 1 mirq=0 mirq=1 obfen pcobfen 0 x kirq is inactive and driven low 1 0 kirq = pcobf@7ff1 1 1 kirq = pcobf@7ffd obfen auxh 0 x mirq is inactive and driven low 1 0 mirq = pcobf@7ffa; status register d5 = user defined 1 1 mirq = pcobf@7ffa; status register d5 = hardware controlled
208 8051 auxobf1 control register aux host data register host isa 0x60 8051 0x7ffa power vcc1 default n/a refer to the auxobf1 description for information on this register. gatea20 hardware speed-up gatea20 is multiplexed onto gpio17 using misc6. the FDC37N972 contains on-chip logic support for the gatea20 hardware speed-up feature. gatea20 is part of the control required to mask address line a20 to emulate 8086 addressing. in addition to the ability for the host to control the gatea20 output signal directly, a configuration bit called "saen" (software assist enable, bit 1 of configuration register 0) is provided; when set, saen allows firmware to con trol the gatea20 output. when saen is set, a 1 bit register as signed to address 7ffbh controls the gatea20 output. the register bit allo cation is shown in table 133 . table 133 - register bit allocation d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x x gatea20 writing a "0" into location d0 causes the gatea20 output to go low, and vice versa. when the register at location 7ffbh is read, all unused bits (d7-d1) are read back as "0". host control and firmware control of gatea20 affect two separate register elements. read back of gatea20 through the use of 7ffbh reflects the present state of the gatea20 output signal: if saen is set, the value read back corresponds to the last firmware-initiated control of gatea20; if saen is reset, the value read back corresponds to the last host-initiated control of gate a20. host control of the gatea20 output is provided by the hardware interpretation of the "gatea20 sequence" (see table 134 ). the foregoing description assumes that the saen configuration bit is reset. when the FDC37N972 receives a "d1" command followed by data (via the host interface), the on-chip hardware copies the value of data bit 1 in the received data field to the gatea20 host latch. at no time during this host-interface transaction will pcobf or the ibf flag (bit 1) in the status register be activated; i.e., this host control of gatea20 is transparent to firmware, with no consequent degradation of overall system per formance. table 134 details the possible gatea20 sequences and the FDC37N972 responses. on vcc1 por, gatea20 will be set. an additional level of control flexibility is offered via a memory-mapped synchron ous set and reset capability. any data written to 7ffeh causes the gatea20 host latch to be set; any
209 data writ ten to 7fffh causes it to be reset. this control mechanism should be used with caution. it was added to augment the "normal" control flow as described above, not to replace it. since the host and the firmware have asynchronous control capability of the host latch via this mech anism, a potential conflict could arise. therefore, after using the 7ffeh and 7fffh addresses, firmware should read back the gatea20 status via 7ffbh (with saen = 0) to confirm the actual gatea20 response. table 134 - gate20 command/data sequence examples sa2 r/w d[0:7] ibf flag gatea20 comments 1 0 1 w w w d1 df ff 0 0 0 q 1 1 gatea20 turn-on sequence 1 0 1 w w w d1 dd ff 0 0 0 q 0 0 gatea20 turn-off sequence 1 1 0 1 w w w w d1 d1 df ff 0 0 0 0 q q 1 1 gatea20 turn-on sequence(*) sa2 r/w d[0:7] ibf flag gatea20 comments 1 1 0 1 w w w w d1 d1 dd ff 0 0 0 0 q q 0 0 gatea20 turn-off sequence(*) 1 1 1 w w w d1 xx** ff 0 1 1 q q q invalid sequence notes: all examples assume that the saen configuration bit is 0. "q" indicates the bit remains set at the previous state. *not a standard sequence. **xx = anything except d1. if multiple data bytes, set ibf and wait at state 0. let the software know something unusual happened. for data bytes sa2=0, only d[1] is used; all other bits are don't care.
210 8051 gatea20 control registers gatea20 host n/a 8051 0x7ffb power vcc1 default 0x01 refer to the gatea20 hardware speed-up description for information on this register. this is a one bit register (bits 1-7=0 on read) setga20l host n/a 8051 0x7ffe (w) power vcc1 default n/a refer to the gatea20 hardware speed-up description for information on this register. a write to this register sets gatea20. rstga20l host n/a 8051 0x7fff (w) power vcc1 default n/a refer to the gatea20 hardware speed-up description for information on this register. a write to this register re-sets gatea20.
211 64&naen sd[7:0] = d1 dff dfe naen&60 after d1 niow d sd[1] fast_gatea20 niow niow_dly niow_dly niow to kreset gen naen&64 niow naen&60 mux cpu_reset bit 1 enab_p92 alt_a20 a20 niow address gatea20 logic trailing edge delay dd1 sd[7:0] = ff sd[7:0] = fe data dd1 niow_dly niow 24mhz d d q q d q d q r r s any write any write vcc delay d nq r ibf bit rstga20l reg setga20l reg port92 reg 0 1 write gatea20 reg read gatea20 reg bit-0 bit-0 d0 d0 gatea20 saen bit-1 of config reg 0 saen q d ibf figure 30 - gatea20 implementation diagram
212 cpu_reset hardware speed-up the alt_cpu_reset bit generates, under program control, the nalt_rst signal, which provides an alternate, means to drive the FDC37N972 cpu_reset pin which in turn is used to reset the host cpu. the nalt_rst signal is internally nanded together with the nkbdreset pulse from the kreset speed up logic to provide an alternate software means of resetting the host cpu. note: before another nalt_rst pulse can be generated, alt_cpu_reset must be cleared to ?0? either by a system reset (nreset_out asserted) or by a write to the port92 register with bit 0 = ?0?. a nalt_rst pulse is not generated in the event that the alt_cpu_reset bit is cleared and set before the prior nalt_reset pulse has completed. kreset pulse gen port92 reg pulse gen cpu_reset enab_p92 fe command bit 0 from kreset speed up logic nalt_rst saen 6us 14 us 6us 14 us figure 31 - cpu_reset implementation diagram port 92 the FDC37N972 supports isa i/o writes to port 92h as a quick alternate mechanism for generating a cpu_reset pulse or controlling the state of gatea20.
213 port 92 register description d7-d2 d1 d0 host r/w r/w r/w r/w bit def 0 reserved alt_gatea20 alt_cpu_reset the port92h register resides at isa address 0x92 and is used to support the alternate reset (nalt_rst) and alternate gatea20 (alt_a20) functions. this register defaults to 0x00 on assertion of nreset_out or on vcc2 power on reset. setting the port 92 enable bit (bit 0 of logical device 7 configuration register 0xf0) enables the port92h register. when port92 is disabled, by clearing the port 92 enable bit, then access to this register is completely disabled (i/o writes to isa 92h are ignored and i/o reads float the system data bus sd[7:0]). when port92h is enabled the bits have the following meaning: d7-d2 reserved a write are ignored and a read return 0. d1 - alt_gatea20 this bit provides an alternate means for system control of the FDC37N972 gatea20 pin. = 0: alt_a20 is driven low = 1: alt_a20 is driven high when port 92 is enabled, writing a 0 to bit 1 of the port92 register forces alt_a20 low. alt_a20 low drivesgatea20 low, if a20 from the keyboard controller is also low. when port 92 is enabled, writing a 1 to bit 1 of the port92 register forces alt_a20 high. alt_a20 high drives gatea20 high regardless of the state of a20 from the keyboard controller. d0 - alt_cpu_reset this bit provides an alternate means to generate a cpu_reset pulse. the cpu_reset output provides a means to reset the system cpu to effect a mode switch from protected virtual address mode to the real address mode. this provides a faster means of reset than is provided through the 8051 keyboard controller. writing a ?1? to this bit will cause the nalt_rst internal signal to pulse (active low) for a minimum of 6 m s after a delay of 14 m s. before another nalt_rst pulse can be generated, this bit must be written back to ?0?.
214 gatea20 the hardware gatea20 state machine returns to state s1 from state s2 when cmd = d1 (figure 32 ). s0 s2 s1 reset cmd !=d1 or data [ibf=1] cmd = ff [ibf=0] cmd !=d1 or cmd !=ff or data [ibf=1] cmd !=d1 [ibf=1] cmd = d1 [ibf=0] cmd = d1 [ibf=0] data [ibf=0, latch din cmd = d1 [ibf=0] notes: gatea20 changes when in s1 going to s2 clock = wrdinb cmd = [sa2=1] data = [sa2=0] gatea20 state machine figure 32 - gatea20 state machine
215 direct keyboard scan the FDC37N972 scanning keyboard controller is designed for intelligent keyboard management in computer applications. by properly configuring gpio4 and gpio5, the FDC37N972 may be programmed to directly control keyboard interface matrixes of up to 16x8. keyboard scan-out register host n/a 8051 0x7f04 (w) power vcc1 default 0x20 d7-d6 d5 d4 d3 d2 d1 d0 8051 r/w w w w w w w w bit def n/a ksen 1 = forces all kso lines to go low d5 and d4 must be ?0? d[3:0] = 0000 kso[0] is asserted low d[3:0] = 0001 kso[1] is asserted low d[3:0] = 0010 kso[2] is asserted low d[3:0] = 0011 kso[3] is asserted low d[3:0] = 1101 kso[13] is asserted low d[3:0] = 1110 kso[14] is asserted low d[3:0] = 1111 kso[15] is asserted low ksen 1 = disable scanning of internal keyboard (all the ksout lines going high) (d4-d0 are don?t cares) 0 = enable scanning of internal keyboard note: setting d[3:0] to 111x puts kso0 - kso13 outputs as hi-z. keyboard scan-in register host n/a 8051 0x7f04 (r) power vcc1 default n/a d7-d0 8051 r r bit description reflects the state of ksi [7:0] the value of the ksi[x] pins can be read through this register. the pin values are latched during the read.
216 external keyboard and mouse interface industry-standard pc/at-compatible keyboards employ a two-wire, bidirectional ttl interface for data transmission. several sources also supply ps/2 mouse products that employ the same type of interface. to facilitate system expansion, the FDC37N972 provides four pairs of signal pins that may be used to implement this interface directly for an external keyboard and mouse. the FDC37N972 has four high-drive, open-drain output (external pull-ups are required), bidirectional port pins that can be used for external serial interfaces, such as isa external keyboard and ps/2-type mouse interfaces. they are kbclk, kbdat, emclk, emdat, imclk, imdat, ps2clk and ps2dat. the following function is assumed to be in the ps/2 port logic: the serial clock lines, kbclk, emclk, imclk and ps2clk, are cleared to a low by vcc2 por. this is so that any power-on self-test completion code transmitted from the serial keyboard will not be missed by the FDC37N972 due to power-up timing mismatches. ps/2 device interface the FDC37N972 has four independent ps/2 serial ports implemented in hardware which are directly controlled by the on chip 8051. the hardware implementation eliminates the need to bit bang i/o ports to generate ps/2 traffic, however bit banging is still available if required. each of the four ps/2 serial channels use a synchronous serial protocol to communicate with the auxiliary device. each ps/2 channel has two signal lines: clock and data. both signal lines are bi-directional and employ open drain outputs capable of sinking 16ma. a pull- up resistor (typically 10k) is connected to the clock and data lines. this allows either the FDC37N972 smsc ps/2 logic or the auxiliary device to control both lines. regardless, the auxiliary device provides the clock for transmit and receive operations. the serial packet is made up of eleven bits, listed in order as they will appear on the data line: start bit, eight data bits (least significant bit first), odd parity, and stop bit. each bit cell is from 60 m s to 100 m s long. the smsc ps/2 and the devil logic interfaces are available in the FDC37N972. the ps2_sel control bit d4 in configuration register 0 (0x7ff4) is used select between these two mutually exclusive options. (see table 90 - configuration register 0 .) many of the smsc ps/2 and the devil logic registers share the same address space in the 8051 mmcrs. these are shown in table 86 between addresses 0x7f41 and 0x7f4f. see 8051 int0 source register on page 172 for a description of the devil logic versus the smsc ps/2 interrupts and a description of the repsective pin mapping.
217 table 135 - pin definitions pin number pin name smsc ps/2 function smsc ps/2 description 45 gpio20 ps2clk channel d serial clock 46 gpio[21] ps2dat channel d serial data 47 imclk imclk channel c serial clock 48 imdat imdat channel c serial data 50 kclk kclk channel b serial clock 51 kdat kdat channel b serial data 52 emclk emclk channel a serial clock 53 emdat emdat channel a serial data all ps/2 serial channel signals (clk and dat) are driven by open collector (type i/od16) drivers pulled to vcc2 (+3.3v nominal) through 10k-ohm resistors. smsc ps/2 logic overview the smsc ps/2 logic allows the host to communicate to any serial auxiliary devices compatible with the ps/2 interface through any one of four channels. the ps/2 logic consists of four identical smsc ps/2 channels, each containing a set of four operating registers. the four channels are ps/2 chan a, ps/2 chan b, ps/2 chan c, and ps/2 chan d. during a reception, the FDC37N972 latches the data on the high to low transition of the clock. during a transmission, the FDC37N972 transitions the data line on the high to low transition of the clock. see figure 33 - smsc ps/2 logic block diagram . notes: 1) each ps/2 channel has the ability to ?busy? the communication link by pulling the clock line low. this is accomplished by simultaneously clearing the ps2_en and wr_clk bits in the control register. 2) each ps/2 channel has the ability to abort, prior to the parity bit (10th bit), the transfer in progress. 3) clock bit time (cycle time) typically varies between 60 and 100 us. the FDC37N972 ps/2 logic is designed such that it is immune to variations in the clock cycle times within the limit of the transfer timeout. 4) once a transmission has begun, the ps/2 `peripheral is allowed up to 300us per bit transfer. if the time between falling clock edges exceeds 300us a transfer timeout occurs resulting in either xmit_timeout or rec_timeout being set along with the generation of an interrupt. 5) once a transmission has started, the ps/2 peripheral has approximately 2ms to complete the transfer. this transfer timeout applies to transmissions as well as receptions. in the case of a transmission(reception), if a 2ms timeout occurs the xmit_timeout(rec_timeout) bit in the status register is set and an interrupt is generated. 6) when the controller is ready to transmit data it floats the data line and drives the clock line low. once data is written to the transmit register the data line is driven low and after a delay the clock line is released (floated) so that the ps/2 peripheral knows data is ready. releasing the clock signals the start of a trasmission. the ps/2 peripheral has 25ms to acknowledge the transmit start condition above by driving the clock line low. if the ps/2 peripheral does not acknowledge in
218 the allotted time then a trasmit timeout occurs: setting the xmit_timeout error bit in the status register and generating an interrupt. 7) by clearing the ps/2 channels ps2_en bit in its control register the ps/2 channel can be operated in a fully software controlled ?bit-bang? mode. this allows operation of auxilliary devices that do not meet standard ps/2 protocol timing handled by the FDC37N972?s ps/2 logic block. 8) see sections 0 through 0 for timing information. ps2_chan_a ps2_chan_b ps2_chan_c ps2_chan_d memory mapped control registers 8051 pdat_a pclk_a pdat_b pclk_b pdat_c pclk_c pdat_d pclk_d figure 33 - smsc ps/2 logic block diagram ps/2 data frame data transmissions to and from the auxilliary device connector on each ps/2 channel consist of an 11- bit data stream sent serially over the data line. the following figure shows the function of each bit. start bit always 0 8 data bits, least sig bit first parity bit odd on xmit prog. on rec. stop bit high on xmit prog. on rec. figure 34 - ps/2 device data stream bit definitions smsc ps/2 memory mapped control registers each smsc ps/2 channel has a separate set of identical control registers: transmit, receive, control,and status. these are shown in table 86 between addresses 0x7f41 and 0x7f4f. the transmit and receive register share the same address (ie. . ps/2 chan a tx/rx) in addition one register is shared by all four channels to provide rx_busy indicators. smsc ps/2 transmit registers the byte written to this register, when ps2_t/r, ps2_en, and xmit_idle are set, is transmitted automatically by the ps/2 channel control logic. if any of these three bits (ps2_t/r, ps2_en, and xmit_idle) are not set, then writes to this
219 register are ignored. on successful completion of this transmission or upon a transmit time- out condition the ps2_t/r bit is automatically cleared and the xmit_idle bit is automatically set. the ps2_t/r bit must be written to a ?1? before initiating another transmission to the remote device. notes: 1) even if ps2_t/r, ps2_en, and xmit_idle are all set, writing the transmit register will not kick off a transmission if rdata_rdy is set. the automatic ps2 logic forces data to be read from the receive register before allowing a transmission. 2) an interrupt is generated on the low to high transition of xmit_idle. 3) all bits of this register are write only. smsc ps/2 receive registers when ps2_en=1 and ps2_t/r=0 the ps2 channel is set to automatically receive data on that channel (both the clk and data lines will float waiting for the peripheral to initiate a reception by sending a start bit followed by the data bits). after a successful reception data is placed in this register and the rdata_rdy bit is set and the clk line is forced low by the ps2 channel logic. rdata_rdy is cleared and the clk line is released to hi-z following a read of this register. this automatically holds off further receive transfers until the 8051 has had a chance to get the data. notes: 1) the receive register is initialized to 0xff after a read or after a timeout has occured. 2) the channel can be enabled to automatically transmit data (ps2_en=1) by setting ps2_t/r while rdata_rdy is set, however a transmission can not be kicked off until the data has been read from the receive register. 3) an interrupt is generated on the low to high transition of rdata_rdy. 4) if a receive timeout (rec_timeout=1) or a transmit timeout (xmit_timeout=1) occurs the channel is busied (clk held low) for 300us (hold time) to guarantee that the peripheral aborts. writing to the transmit register will be allowed, however the data written will not be transmitted until the hold time expires. 5) all bits in this register are read only
220 smsc ps/2 control registers table 136 - smsc ps/2 control registers (a - d) host address - 8051 address 0x7f42 (chan a), 0x7f46 (chan b), 0x7f4a (chan c), 0x7f4e (chan d) power vcc2 default 0x40 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 type r/w r/w r/w r/w r/w r/w r/w r/w bit name wr_clk wr_data stop parity ps2_en ps2_t/r default = 0x40 on vcc2 por only. note: there are four ps/2 control registers, one for each channel. ps2_t/r ps/2 channel transmit/receive (default = 0). this bit is only valid when ps2_en=1 and sets the ps2 logic for automatic transmission or reception when ps2_t/r equals ?1? or ?0? respectively. when set the ps/2 channel is enabled to transmit data. to properly initiate a transmit operation this bit must be set prior to writing to the transmit register; writes are blocked to the transmit register when this bit is not set. upon setting the ps2_t/r bit the channel will drive its clk line low and then float the data line and hold this state until a write occurs to the transmit register or until the ps2_t/r bit is cleared. writing to the transmit register initiates the transmit operation. FDC37N972 drives the data line low and, within 80ns, floats the clock line (externally pulled high by the pull- up resistor) to signal to the external ps/2 device that data is now available. the ps2_t/r bit is cleared on the 11th clock edge of the transmission or if a transmit timeout error condition occurs. note: if the ps2_t/r bit is set while the channel is actively receiving data prior to the leading edge of the 10th (parity bit) clock edge the receive data is discarded. if this bit is not set prior to the 10th clock signal then the receive data is saved in the receive register. when the ps2_t/r bit is cleared the ps/2 channel is enabled to receive data. upon clearing this bit, if rdata_rdy=0, the channel?s clk and data will float waiting for the external ps/2 device to signal the start of a transmission. if the ps2_t/r bit is set while rdata_rdy=1 then the channel?s data line will float but its clk line will be held low, holding off the peripheral, until the receive register is read.
221 ps2_en ps2 channel enable (default = 0). when ps2_en=1 the ps/2 state machine is enabled allowing the channel to perform automatic reception or transmission depending on the bit value of ps2_t/r. when ps2_en = 0, the channel?s automatic ps/2 state machine is disabled and the channel can be bit-banged through the wr_data and wr_clk bits in the contol register and the rd_data and rd_clk bits in the status register. thus, when ps2_en=0, the channel?s clk and data lines are forced to the level specified in the control register wr_clk and wr_data bits. note: if the ps2_en bit is cleared prior to the leading edge (falling edge) of the 10th (parity bit) clock edge the receive data is discarded (rdata_rdy remains low). if the ps2_en bit is cleared following the leading edge of the 10th clock signal then the receive data is saved in the receive register (rdata_rdy goes high) assuming no parity error. parity bits [3:2] of the control register are used to set the parity expected by the ps/2 channel state machine. these bits are therefore only valid when ps2_en=1. bits[3:2] = 00 : receiver expects odd parity (default). = 01 : receiver expects even parity. = 10 : receiver ignores level of the parity bit (10th bit is not interpreted as a parity bit). = 11 : reserved. stop bits [5:4] of the control register are used to set the level of the stop bit expected by the ps/2 channel state machine. these bits are therefore only valid when ps2_en=1. bits[5:4] = 00 : receiver expects an active high stop bit. = 01 : receiver expects an active low stop bit. = 10 : receiver ignores the level of the stop bit (11th bit is not interpreted as a stop bit). = 11 : r eserved. wr_data write data bit: when ps2_en=1, writes to the wr_data bit are accepted but result in no action other than setting or clearing this bit. when ps2_en=0, setting this bit to a 1 or 0 either floats or drives low the ps/2 channel?s serial data pin. this bit is used for transmitting bit-banged data over the ps2 channel. bit-banging of the ps/2 channel is enabled when ps2_en= 0. note : while the hold timeout is in effect (300us following a receive or transmit timeout) writes to this bit are blocked. wr_clk write clk bit: when ps2_en=1, writes to the wr_clk bit are accepted but result in no action other than setting or clearing this bit. when ps2_en=0, setting this bit to a 1 or 0 either floats or drives low the ps/2 channel?s serial clk pin. bit-banging of the ps/2 channel is enabled when the ps2_en bit is set to 0.
222 smsc ps/2 status registers note : while the hold timeout is in effect (300us following a receive or transmit timeout) writes to this bit are blocked. note : when ps2_en = 0, high to low transitions on the clk pin caused by the peripheral will generate a ps2 chan interrupt. a timeout event or writing this bit low will not cause an interrupt. the default for the wr_data bit d6 in the four smsc ps/2 control registers is ?1?. the default in earlier devices is ?0? ( table 136 ). the vcc2 power-on default for each control register is 40h. table 137 - smsc ps/2 staus registers (a - d) host address - 8051 address 0x7f43 (chan a), 0x7f47 (chan b), 0x7f4b (chan c), 0x7f4f (chan d) power vcc2 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 type r r r r r r r r bit name rd_clk rd_data xmit_ timeout xmit_idle fe pe rec_ timeout rdat _rdy default = 0x40 on vcc2 por only. note: there are four ps/2 status registers, one for each channel. note : xmit_timeout, fe, pe, rec_timeout, rdata_rdy are cleared to zero upon a read of this register.
223 rdata_rdy receive data ready: under normal operating conditions, this bit is set following the falling edge of the 11th clock given successful reception of a data byte from the ps/2 peripheral (i.e., no parity, framing, or receive timeout errors) and indicates that the received data byte is available to be read from the receive register. this bit may also be set in the event that the ps2_en bit is cleared following the 10th clk edge (see the ps2_en bit description for further details). reading the receive register clears this bit. note : an interrupt is generated on the low to high transition of the rdata_rdy bit. rec_timeout under ps2 automatic operation, ps2_en=1, this bit is set on one of 4 receive error conditions, and in additon the channel?s clk line is automatically pulled low and held for a period of 300us following assertion of the rec_timeout bit : 1) when the receiver bit time (time between falling edges) exceeds 300us. 2) if the time from the 1st (start) bit to the 10th (parity) bit exceeds 2ms. 3) on a receive parity error along with the parity error (pe) bit. 4) on a receive framing error due to an incorrect stop bit along with the framing error (fe) bit. the rec_timeout bit is cleared when the status register is read. note : an interrupt is generated on the low to high transition of the rec_timeout bit. pe parity error: when receiving data the parity bit is clocked in on the falling edge of the 10th clk edge. if the channel has been set to expect either even or odd parity and the 10th bit is contrary to the expected parity, then the pe and rec_timeout bits are set following the falling edge of the 10th clk edge and an interrupt is generated. fe framing error: when receiving data the stop bit is clocked in on the falling edge of the 11th clk edge. if the channel has been set to expect either a high or low stop bit and the 11th bit is contrary to the expected stop polarity, then the fe and rec_timeout bits are set following the falling edge of the 11th clk edge and an interrupt is generated. xmit_idle transmiter idle: when low, the xmit_idle bit is a status bit indicating that the ps2 channel is actively transmitting data to the ps2 peripheral device. writing to the transmit register when the channel is ready to transmit will cause the xmit_idle bit to deassert and remain deasserted until one of the following conditions occur: 1) the falling edge of the 11th clk; upon a transmit timeout condition (xmit_timeout goes high); 2) upon the ps2_t/r bit being written to 0; 3) upon the ps2_en bit being written to 0. note : an interrupt is generated on the low to high transition of xmit_idle. xmit_timeout this bit is set on one of 3 transmit conditions, and in additon the channel?s clk line is automatically pulled low and held for a period of
224 300us following assertion of the xmit_timeout bit during which time the ps2_t/r is also held low : when the transmitter bit time (time between falling edges) exceeds 300us. when the transmitter start bit is not received withing 25ms from signaling a transmit start event. if the time from the 1st (start) bit to the 10th (parity) bit exceeds 2ms. rd_data read data bit: reading this bit returns the current level of the ps2 channel?s serial data pin. this bit is used for receiving bit-banged data over the ps2 channel. bit-banging of the ps2 channel is enabled when the ps2_en bit is set to 0. to receive data properly using this bit, ps2_en must be set to 0 and the wr_data bit in the ps2 channel?s control register must be set to 1. rd_clk read clk bit: reading this bit returns the current level of the ps2 channel?s serial clk pin. this bit is used when receiving bit-banged data over the ps2 channel. bit-banging of the ps2 channel is enabled when the ps2_en bit is set to 0. to receive bit banged data properly the ps2_en must be set to 0 and the wr_clk bit in the ps2 channel?s control register must be set to 1. note : when ps2_en = 0, high to low transitions on the clk pin will generate a ps2 chan interrupt. a timeout event or writing this bit low will not cause an interrupt. note : when ps2_en=1, bit-banging is disabled for any of the following 3 conditions: time-out is active. 300us following a time-out (hold time). rdata_rdy = 1. smsc ps/2 status_2 registers the ps/2_status_2 register supports the rx_busy indicators for each of the four ps/2 channels (a - d) when a rx_busy bit is set the associated channel is actively receiving ps/2 data; when a rx_busy bit is clear the channel is idle. table 138 - smsc ps/2_status_2 register host address` - 8051 address 0x7f48 power vcc2 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 type r r r r r r r r
225 programmer?s note : always check that an smsc ps/2 channel is idle, i.e. the rx_busy bit is ?0?, before attempting to transmit on that channel. receive data may or may not be lost by setting an smsc ps/2 channel to transmit while the rx_busy bit is asserted depending where in the message frame the tranmit mode change occurs. devil logic overview the devil ps/2 logic allows the host to communicate to any serial auxiliary devices compatible with the ps/2 interface through any one of four ports: em, kb, im and ps2. there are two identical ps/2 channels, each containing a set of five operating registers. channel 1 (ps/2 port 1) consists of ports em and kb and channel 2 (ps/2 port 2) consists of ports im and ps2. the FDC37N972 latches data on the high to low transition of the clock. the devil ps/2 logic commands the devil ps/2 logic supports three commands: transmit, receive, and inhibit. notes: 1) the hardware state machine requires that you read any pending command response byte from the input register before you send an inhibit command to the device. since only one response byte is allowed to be automatically received, there is no need to inhibit the port before you read the response. 2) after sending a transmit or receive command to the control register, do not read the status register until the ps/2 interrupt flag is set. if you read the status register to check the busy bits, the bit counter will reset and you will either get receive time-outs (all bits not received within 2 ms), or you will get parity errors. if there is a receive error, the busy bit can be used to determine which device was sending when the error occurred. if there is a transmit error, the enable bit in the control register can be used to determine which device was selected. 3) if your ps/2 code is interrupt driven, is best to send the inhibit command while the interrupts are enabled so any byte being received can finish and get picked up by the interrupt handler. this is necessary because a receive may have been in progress when the inhibit command was issued, and a receive will complete if the parity bit is reached. 4) if there is a request to send (rts) time- out or other condition which results in no byte being received from the devil ps/2 device, there will be no device 'data ready' flag set in the status register. it will be necessary to read the device enable bits in the status register, or use some other means to remember which. the devil ps/2 logic transmit command the devil ps/2 serial protocol requires that the auxiliary device respond to all transmissions that it receives. the response is usually a 0xfa , 0xfe, 0xfc or 0xee. the response is stored in the devil ps/2 ports receive register. thus, after each transmission the receive register should contain some response byte. when sending a byte to a devil ps/2 device, two writes to the control register are required to avoid race conditions: first the device select bit(s) (bits[4:3]) in the control register must be set, clearing the command bits[2:0]; then another write to the control register selecting
226 one command, and preserving the device select bits. the devil ps/2 logic will assume that the byte being sent is a 'command', and will automatically go into receive mode for a single response byte. the devil ps/2 logic must be placed into receive mode to receive additional response bytes. an error will be reported if the device does not start clocking out the command byte within 15 ms, or if the device does not send a response within 32 ms of receiving the command. the devil ps/2 logic will cause an interrupt after the response byte is received, or if there is a send or receive time-out. the devil ps/2 logic drives the clock line low and then floats the data line when the port is selected to transmit. writing to the transmit register initiates the transmit operation. the data line is driven low and, within 80ns, the clock line is floated (externally pulled high by the pull-up resistor). the auxiliary device recognizes this as the start bit, and responds by providing the eleven clocks (each clock corresponds to a bit). the logic provides a 3.2 m s bit hold time. if the auxiliary device did not respond within 15 ms after the start bit, transmit is terminated and error bit of the status register and the rtstimout bit of the error register are set. the auxiliary device has 2 ms to complete the transmission or the devil ps/2 logic will set the error bit of the status register and the xmttimout bit of the error register. if the transmission is successful, the clock and data lines are floated waiting for the auxiliary device to send the response packet. if the first byte of the response packet is not received within 32 ms, the error bit of the status register is set, the restimout bit of the error register is set. if, on the other hand, the response packet is received and there are no errors, the devil ps/2 logic sets the ready bit of the status register, clears the error bit of the status register, and clears the error register. the receive register contains the received response byte. the devil ps/2 logic receive command when receiving scan codes or mouse packets, select one or both devil ps/2 devices in the control register (bits[4:3]), clearing the command bits[2:0]. then do another write setting the receive command bit while preserving the device select bits. the devil ps/2 logic will only let one device send at a time (whichever starts sending first), and will cause an interrupt for each received byte. reading the byte from the receive register causes the devil ps/2 logic to go into receive mode again. the devil ps/2 logic floats the devil ps/2 port?s clock and data line when the port is selected to receive. the auxiliary device initiates the transfer by driving the data line low and 12 m s later driving the clock low. the devil ps/2 logic recognizes this as a start bit and sets the busy bit. the auxiliary device proceeds by transmitting ten more bits to the devil ps/2 logic. the devil ps/2 logic latches the data on the high to low transition of the clock. after the stop bit, the devil ps/2 logic clears the busy bit and drives the clock line low until the receive register is read by the 8051. if there is no error in the transfer, the devil ps/2 logic sets the ready bit of the status register, clears the error bit of status register, and clears the error register. if, however, the receive operation does not complete in 2 ms of receiving a start bit, the error bit of the status register is set together with the rectimout bit of the error register, and the ready bit is not set. note that the logic can be left in receive mode indefinitely and is normally used to receive keyboard scan codes and mouse packets.
227 the devil ps/2 logic inhibit command when you abort a transmission from a devil ps/2 device, it is necessary to hold the clock line low for at least 100 us in order for the device to note that the transmission has been aborted. this 100 us low clock time is called a device 'inhibit'. when you want to perform the inhibit command, select one or both devil ps/2 devices in the control register, clearing the command bits. then do another write setting the inhibit command bit while preserving the device select bits. the devil ps/2 logic will hold the device clock lines low and count down 100 us, then it will generate an interrupt to indicate that the time-out is over. the interrupt handler should then clear the inhibit command bit in the control register. after an inhibit, the device clock lines will remain low until the next transmit or receive command. note that if the device is receiving a byte when the inhibit command is sent, and the parity bit has already been started, the device will complete the receipt and set the ready bit before the inhibit takes effect, so it is necessary to check for data even when the inhibit done bit is set. devil ps/2 memory mapped control registers each devil ps/2 channel has a separate set of identical control registers: control, status, error status, transmit, and receive. these are shown in table 86 between addresses 0x7f41 and 0x7f4f. devil ps/2 control registers table 139 - devil ps/2 control registers (port1 & port2) host address - 8051 address 0x7f41 (port 1), 0x7f49 (port 2), power vcc2 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 type r r r r/w r/w r/w r/w r/w bit name port1 (port2) res res res em_en (im_en) kb_en (ps2_en) inhibit rx_en tx_en
228 table 140 - ps/2 port1 (port2) control register operation inhibit rx_en tx_en em_en (im_en) kb_en (ps2_en) operation status 0 0 1 0 1 transmission sent to keyboard, echo cmd received 0 0 1 1 0 transmission sent to ext mouse, echo cmd rcvd 0 0 1 1 1 transmission inhibited, rts_timeout error, (illegal state) 0 1 0 0 1 data received from keyboard, transmission initiated by keyboard. 0 1 0 1 0 data received from mouse, transmission initiated by mouse. 0 1 0 1 1 data received from keyboard and mouse, transmissions are initiated by keyboard and mouse and interlaced to ps/2 port1 receive register. 1 x x x x em and kb ps/2 interfaces are disabled. data written to the ps2 port1 transmit register is not transmitted and no data is received from the external mouse or keyboard. notes: 1. the operation of the ps/2 port2 control register is similar for the im and ps/2 devices. 2. only one of bits d2-d0 can be set to one.
229 devil ps/2 status registers table 141 - devil ps/2 status registers (port1 & port2) host address - 8051 address 0x7f42 (port 1), 0x7f4a (port 2), power vcc2 default 0x40 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 type r r r r r r r r bit name port1 (port2) res res em_busy (im_busy) kb_busy (ps2_busy) inhibit done em_drdy (im_drdy) kb_drdy (ps2_drdy) error error this bit is set in the event of a transmit or receive error condition on either the em or kb ps/2 ports or the im or ps/2 ports. the cause of the error can be determined by reading the ps/2 port1 or ps/2 port2 status register. kb_drdy this bit is set if kb_en is set and a character has been received successfully from the ps/2 kb port. this bit is cleared when the data has been read from the ps/2 port1 receive register. em_drdy this bit is set if em_en is set and a character has been received successfully from the ps/2 em port. this bit is cleared when the data has been read from the ps/2 port1 receive register. ps2_drdy this bit is set if ps2_en is set and a character has been received successfully from the ps/2 port. this bit is cleared when the data has been read from the ps/2 port2 receive register. im_drdy this bit is set if im_en is set and a character has been received successfully from the ps/2 im port. this bit is cleared when the data has been read from the ps/2 port2 receive register.
230 inhibit done this bit is set when the inhibit bit of the control register was set and the 100 us inhibit sequence has finished. kb_busy this bit is set when the ps/2 kb port is actively receiving a character. em_busy this bit is set when the ps/2 em port is actively receiving a character. ps2_busy this bit is set when the ps/2 port is actively receiving a character. im_busy this bit is set when the ps/2 im port is actively receiving a character. note: 1) on receive the busy bit is set while receiving the first data bit and cleared while receiving the parity bit. on transmit, the busy bit is not set at all. 2) the operation of the ps/2 port2 status register is similar for the im and ps/2 devices.
231 devil ps/2 error status table 142 - devil ps/2 error status registers (port1 & port2) host address - 8051 address 0x7f43(port 1), 0x7f4b(port 2), power vcc2 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 type r r r r r r r r bit name res res res parity res_ timeou t rec_ timeou t rts_ timeou t xmt_ timeout xmt_timeout (transmit_timeout) is set when the device fails to clock out a command within 2ms of clocking out the start bit. rts_timeout (readytosend_timeout) is set when the device fails to start clocking out the command within 15 ms. rec_timeout (receiver_timeout) is set when the device does not finish sending a byte within 2 ms of sending the start bit. res_timeout (response_timeout) is set when the response to a command is not received within 32 ms. parity the ps/2 ports use odd parity, in the event of a receive parity error this bit is set.
232 devil ps/2 transmit registers table 143 - devil ps/2 transmit registers (port1 & port2) host address - 8051 address 0x7f44(port 1), 0x7f4c(port 2), power vcc2 default 0x00 the byte written to the ps/2 port1(port2) transmit register is immediately transmitted onto the enabled ps/2 port1/port2 provided that the ps/2 port1(port2) inhibit bit is not set and that both ps/2 port1and port2 devices are not enabled for transmit at the same time. this register is write only. devil ps/2 receive registers table 144 - devil ps/2 receive registers (port1 & port2) host address - 8051 address 0x7f45(port 1), 0x7f4d(port 2), power vcc2 default 0x00 if kb_en, and/or em_en is set and ps/2 port1 rx_en is set any successfully received characters over the kb and/or the em ps/2 port are placed into this register and the em_drdy or kb_drdy ps/2 port1 status bit is set. similarly, if ps2_en and/or im_en is set and ps/2 port2 rx_en is set any successfully received characters over the ps2 and/or im ps2 ports are placed into this register and the ps2_drdy or im_drdy ps/2 port2 status bit is set.
233 access.bus background the FDC37N972 supports access.bus. access.bus is a serial communication protocol between a computer host and its peripheral devices. it provides a simple, uniform and inexpensive way to connect peripheral devices to a single computer port. a single access.bus on a host can accommodate up to 125 peripheral devices. the access.bus protocol includes a physical layer based on the i 2 c tm serial bus developed by philips, and several software layers. the software layers include the base protocol, the device driver interface, and several specific device protocols. for a description of the access.bus protocol, please refer to the access.bus specifications version 2.2, february 1994, available from the access.bus industry group (abig). the access.bus interface is based on the pcf8584 controller. the registers are mapped into the 8051?s external memory mapped register space. the addresses for the registers are shown in table 145 - access.bus register addresses. table 146 - access.bus register addresses address (note 1) access rights register 7f31h w control s1 7f31h r status s1 7f32h r/w own address s0? 7f33h r/w data s0 7f34h r/w (1) clock s2 note: these registers are only directly accessible by the 8051 and reside within the 8051?s external memory mapped data address space. note 1: bits 2 through 6 are read only reserved.
234 register description the access.bus interface has four internal register locations. two of these, own address register s0? and clock register s2, are used for initialization of the chip. normally they are only written once directly after resetting of the chip. the other two registers, the data register s0, and the control/status register s1, (which functions as a double register) are used during actual data transmission/reception. register s0 performs all serial-to-parallel interfacing with the access.bus. register s1 contains access.bus status information required for bus access and/or monitoring. access.bus control/status register s1 the control/status register controls the access.bus operation and provides status information. this register has separate read and write functions for all bit positions. the write-only section provides register access control and control over access.bus signals, while the read-only section provides access.bus status information. access.bus control/status register s1: control d7 d6 d5 d4 d3 d2 d1 d0 r/w w w w w w w w w bit def pin es0 reserved reserved eni sta sto ack status d7 d6 d5 d4 d3 d2 d1 d0 r/w r r r r r r r r bit def pin 0 sts ber lrb aas lab nbb bit definitions register s1 control section the write-only sections of s1 enables access to registers s0, s1 and s2, and also control of access.bus operation. bit 7 pin pending interrupt not. writing the pin bit to a logic ?1? deasserts all status bits except for the nbb (bus busy) - nbb is not affected. the pin bit is a self-clearing bit. writing this bit to a logic ?0? has no effect. this may serve as a software reset function. bit 6 eso enable serial output. eso enables or disables the serial access.bus i/o. when eso is high, access.bus communication is enabled; communication with serial shift register s0 is enabled and the s1 bus status bits are made available for reading. with eso = 0, bits eni, sta, sto and ack of s1 can be read for test purposes. bit 5 and 4 reserved bit 3 eni this bit enables the internal interrupt, nint, which is generated when the pin bit is active (logic 0). bit 2 and 1 sta and sto these bits control the generation of the access.bus start condition and transmission of slave address and r/nw bit, generation of repeated start condition, and generation of the stop condition (see table 147 ).
235 table 147 - instruction table for serial bus control sta sto present mode function operation 1 0 slv/rec start transmit start+address, remain mst/trm if r/nw=0; go to mst/rec if r/nw=1. 1 0 mst/trm repeat start same as for slv/rec 0 1 mst/rec; mst/trm stop read; stop write transmit stop go to slv/rec mode; note 1 1 1 mst data chaining send stop, start and address after last master frame without stop sent; note 2 0 0 any nop no operation; note 3 note 1: i n master receiver mode, the last byte must be terminated with ack bit high (?negative acknowledge?). note 2: if both sta and sto are set high simultaneously in master mode, a stop condition followed by a start condition + address will be generated. this allows ?chaining? of transmissions without relinquishing bus control. note 3: all other sta and sto mode combinations not mentioned in table 146 are nops. bit 0 ack this bit must be set normally to logic ?1?. this causes the access.bus to send an acknowledge automatically after each byte (this occurs during the 9th clock pulse). the bit must be reset (to logic ?0?) when the access.bus controller is operating in master/receiver mode and requires no further data to be sent from the slave transmitter. this causes a negative acknowledge on the access.bus, which halts further transmission from the slave device. register s1 status section the read-only section of s1 enables access to access.bus status information. bit 7 pin pending interrupt not. this bit is a status flag which is used to synchronize serial communication and is set to logic ?0? whenever the chip requires servicing. the pin bit is normally read in polled applications to determine when an access.bus byte transmission/reception is completed. when acting as transmitter, pin is set to logic ?1? (inactive) each time s0 is written. in receiver mode, the pin bit is automatically set to logic ?1? each time the data register s0 is read. after transmission or reception of one byte on the access.bus (nine clock pulses, including acknowledge) the pin bit will be automatically reset to logic ?0? (active) indicating a complete byte transmission/reception. when the pin bit is subsequently set to logic ?1? (inactive) all status bits will be reset to ?0? on a ber (bus error) condition. in polled applications, the pin bit is tested to determine when a serial transmission/reception has been completed. when the eni bit (bit 4 of write-only section of register s1) is also set to logic ?1? the hardware interrupt is enabled. in this case, the pi flag also triggers and internal
236 interrupt (active low) via the nint output each time pin is reset to logic ?0?. when acting as a slave transmitter or slave receiver, while pin = ?0?, the chip will suspend access.bus transmission by holding the scl line low until the pin bit is set to logic ?1? (inactive). this prevents further data from being transmitted or received until the current data byte in s0 has been read (when acting as slave receiver) or the next data byte is written to s0 (when acting as slave transmitter). pin bit summary the pin bit can be used in polled applications to test when a serial transmission has been completed. when the eni bit is also set, the pin flag sets the internal interrupt via the nint output. in transmitter mode, after successful transmission of one byte on the access.bus the pin bit will be automatically reset to logic ?0? (active) indicating a complete byte transmission. in transmitter mode, pin is set to logic ?1? (inactive) each time register s0 is written. in receiver mode, pin is set to logic ?0? (inactive) on completion of each received byte. subsequently, the scl line will be held low until pin is set to logic ?1?. in receiver mode, when register s0 is read, pin is set to logic ?1? (inactive). in slave receiver mode, an access.bus stop condition will set pin=0 (active). pin=0 if a bus error (ber) occurs. bit 6 reserved , logic 0. bit 5 sts when in slave receiver mode, this flag is asserted when an externally generated stop condition is detected (used only in slave receiver mode). bit 4 ber bus error; a misplaced start or stop condition has been detected. resets nbb (to logic ?1?; inactive), sets pin = ?0? (active). bit 3 lrb/ad0 last received bit or address 0 (general call) bit. this status bit serves a dual function, and is valid only while pin=0: lrb holds the value of the last received bit over the access.bus while aas=0 (not addressed as slave). normally this will be the value of the slave acknowledgment; thus checking for slave acknowledgment is done via testing of the lrb. ado; when aas = ?1? (addressed as slave condition) the access.bus controller has been addressed as a slave. under this condition, this bit becomes the ad0 bit and will be set to logic ?1? if the slave address received was the ?general call? (00h) address, or logic ?0? if it was the access.bus controller?s own slave address. bit 2 aas addressed as slave bit. valid only when pin=0. when acting as slave receiver, this flag is set when an incoming address over the access.bus matches the value in own address register s0? (shifted by one bit) or if the access.bus ?general call? address (00h) has been received (?general call? is indicated when ad0 status bit is also set to logic ?1?).
237 bit 1 lab lost arbitration bit. this bit is set when, in multi-master operation, arbitration is lost to another master on the access.bus. bit 0 nbb bus busy bit. this is a read-only flag indicating when the access.bus is in use. a zero indicates that the bus is busy, and access is not possible. this bit is set/reset (logic ?1?/logic ?0?) by start/stop conditions. own address register s0? when the chip is addressed as slave, this register must be loaded with the 7-bit access.bus address to which the chip is to respond. during initialization, the own address register s0? must be written to, regardless whether it is later used. the addressed as slave (aas) bit in status register s1 is set when this address is received (the value in s0 is compared with the value in s0?). note that the s0 and s0? registers are offset by one bit; hence, programming the own address register s0? with a value of 55h will result in the value aah being recognized as the chip?s access.bus slave address. after reset, s0? has default address 00h. table 148 - a ccess.bus own address register s0 own addr d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w bit def reserved slave address 6 slave address 5 slave address 4 slave address 3 slave address 2 slave address 1 slave address 0 data shift register s0 register s0 acts as serial shift register and read buffer interfacing to the access.bus. all read and write operations to/from the access.bus are done via this register. access.bus data is always shifted in or out of shift register s0. in receiver mode the access.bus data is shifted into the shift register until the acknowledge phase. further reception of data is inhibited (scl held low) until the s0 data shift register is read. in the transmitter mode data is transmitted to the access.bus as soon as it is written to the s0 shift register if the serial i/o is enabled (eso=1). table 149 - access.bus data register s0 data d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w clock register s2 register s2 controls the selection of the internal chip clock frequency used for the access.bus block. this determines the scl clock frequency generated by the chip. the selection is made via bits[2:0] (see table 151 - internal clock rates and access.bus data rates ).
238 table 150 - access.bus clock register d7 d6-d2 d1 d0 8051 r/w r/w r r/w r/w ab_rst (note 1) reserved 00 - clock off (default) 01 - 32 khz clock 10 - 8051 clock 11 - 24 mhz clock (see table below) note 1: access.bus reset, not self-clearing, must be written high and then written low. bit 7 ab_rst: (access.bus reset) setting this bit re-initializes all logic and registers in the access.bus block. table 151 - internal clock rates and access.bus data rates access bus clock clock rate data rate nominal high nominal low minimum high d[1-0] 00 off 10 ring osc f/240 96/f 144/f 18/f ring osc=4 mhz 16.7 khz 24 m s 36 m s 4.5 m s ring osc=6 mhz 25 khz 16 m s 24 m s 3 m s ring osc=8 mhz 33.3 khz 12 m s 18 m s 2.25 m s 10 12mhz 50 khz 8 m s 12 m s 4 m s 10 14.3 mhz 60 khz 6.7 m s 10.1 m s 4 m s 10 16 mhz 67 khz 6 m s 9 m s 4 m s 11 24 mhz 100 khz 4 m s 6 m s 4 m s f = frequency of the ring oscillator. access.bus interface description the access.bus interface is fully and directly controlled by the on-chip 8051 through its set of on-chip memory mapped control registers. the access.bus logic is based on the pcf8584 i2c controller and is powered on the vcc1 powerplane to provide the ability to wake-up the 8051 on an access.bus event.
239 memory mapped control registers table 152 - access.bus control register host n/a 8051 0x7f31 (w) power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 8051 r/w w w w w w w w w bit def pin es0 reserved reserved eni sta sto ack bit 7 pin: pending interrupt not - writing this bit to a logic ?1? deasserts all status bits except for nbb (bus busy), nbb is not affected. this is a self-clearing bit. writing this bit to a logic ?0? has no effect. table 153 - access.bus status register host n/a 8051 0x7f31 (r) power vcc1 default 0x81 d7 d6 d5 d4 d3 d2 d1 d0 8051 r/w r r r r r r r r bit def pin 0 sts ber lrb aas lab nbb access.bus own address register host n/a 8051 0x7f32 power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 8051 r/w r/w r/w r/w r/w r/w r/w r/w r/w bit def reserved slave address 6 slave address 5 slave address 4 slave address 3 slave address 2 slave address 1 slave address 0
240 access.bus data register host n/a 8051 0x7f33 power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 8051 r/w r/w r/w r/w r/w r/w r/w r/w r/w access.bus clock register host n/a 8051 0x7f34 power vcc1 default 0x00 access.bus clock d7 d6-d2 d1 d0 8051 r/w r/w r r/w r/w ab_rst* reserved 00 - clock off (default) 10 - 8051 clock 11 - 24 mhz clock (*) access.bus reset, not self-clearing, must be written high and then written low. bit 7 ab_rst: (access.bus reset) setting this bit re-initializes all logic and registers in the access.bus block. table 154 - access.bus clock rates access. bus clock clock rate data rate nominal high nominal low minimum high d[1:0] 00 off 10 ring osc f/240 96/f 144/f 18/f ring osc=4 mhz 16.7 khz 24 m s 36 m s 4.5 m s ring osc=6 mhz 25 khz 16 m s 24 m s 3 m s ring osc=8 mhz 33.3 khz 12 m s 18 m s 2.25 m s 10 12 mhz 50 khz 8 m s 12 m s 4 m s 10 14.3 mhz 60 khz 6.7 m s 10.1 m s 4 m s 10 16 mhz 67 khz 6 m s 9 m s 4 m s 11 24 mhz 100 khz 4 m s 6 m s 4 m s f = frequency of the ring oscillator.
241 second i 2 c bus interface overview a second i 2 c controller (access.bus 2) is in the FDC37N972. access.bus 2 is powered by vcc1. there are 5 memory-mapped control registers to support the access.bus 2 controller (table 155 to table 159 ). the two access.bus 2 controller pins, ab2_data and ab2_clk, are multiplexed on gpio11 and gpio12 (see multifunction pin on page 271). an i 2 c input clock divider bit d2 is added to the access.bus clock registers (see section 0 i2c clock divider bit , below). memory mapped control registers table 155 - access.bus 2 control register host address 8051 address power plane default - 0x7f67 (w) vcc1 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 type w w w w w w w w bit name pin es0 reserved eni sta sto ack table 156 - access.bus 2 status register host address 8051 address power plane default - 0x7f67 (r) vcc1 0x81 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 type r r r r r r r r bit name pin 0 sts ber lrb aas lab nbb
242 table 157 - access.bus 2 own address register host address 8051 address power plane default - 0x7f68 vcc1 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 type r r/w r/w r/w r/w r/w r/w r/w bit name reser ved slave addr. 6 slave addr. 5 slave addr. 4 slave addr. 3 slave addr. 2 slave addr. 1 slave addr. 0 table 158 - access.bus 2 data register host address 8051 address power plane default - 0x7f69 vcc1 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 type r/w r/w r/w r/w r/w r/w r/w r/w bit name d7 d6 d5 d4 d3 d2 d1 d0 table 159 - access.bus 2 clock register host address 8051 address power plane default - 0x7f6a vcc1 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 type r/w r r r r r r/w r/w bit name ab_rst reserved clk_d iv clock select
243 i 2 c clock divider bit an input clock divider bit d2 is added to the access.bus clock registers 0x7f34 (table 160 ) and 0x7f6a (table 159 ). the clock divider bit clk_div affects all i 2 c clock inputs. when clk_div is ?1?, the i 2 c input clock is divided by 2. when clk_div is ?0?, the i 2 c input clock is not divided. t able 160 - access.bus 1 clock register host address n/a 8051 address 0x7f34 power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 type r/w r r r r r/w r/w r/w bit name ab_rst reserved clk_div clock select clock select encoding the encoding for the two clock select bits is shown in table 161 . the clock select bits are located in the access.bus 1 clock register ( table 160 ) and the access.bus 2 clock register ( table 159 ). table 161 - access.bus clock select bit encoding clock select bits FDC37N972 d1 d0 0 0 clock off 0 1 reserved 1 0 8051 clock 1 1 24 mhz clock
244 mailbox register interface overview the mailbox registers interface provides a standard run-time mechanism for the host to communicate with the 8051 and other logical components in the FDC37N972. the mailbox registers interface includes a total of 44 index- addressable 8-bit registers (table 162 ) and two 8-bit host access ports (table 164 ). thirty-two of these 44 registers are 8051 mailbox registers. the mailbox registers interface host access ports are run-time registers that occupy two addresses in the system i/o space. the access ports are used by the host to read and write the 44 registers. the access ports base address is determined by the mailbox registers interface base address that is initialized in logical device number 9 in FDC37N972 configuration registers cr60 and cr61 (table 163 ). the 32 mailbox registers as well as the pwm0, pwm1, and fan control registers are directly addressable by the 8051 through memory- mapped control registers (see table 86 - 8051 on-chip external memory mapped registers on page 159). in this specification, the registers in the mailbox registers interface are identified by the prefix mbx in front of a hexadecimal index address. table 162 below summarizes the 44 registers in the mailbox registers interface. table 162 - mailbox registers interface total regs. mailbox index address system r/w 8051 addr. (7f00+) 8051 r/w power plane vcc 1 por vcc 2 por zero wait state (1) n o t e s system-to- 8051 mailbox register 0 1 mbx82h r/w 08h rc vcc1 00 y 2 8051-to- system mailbox register 1 1 mbx83h rc 09h r/w vcc1 00 y 3 mailbox register [2- f] 14 mbx 84h- 91h r/w 0ah - 17h r/w vcc1 00h y pwm0 register 1 mbx92h r/w 25h r/w vcc1 00h y pwm1 register 1 mbx93h r/w 26h r/w vcc1 00h y 8051stp_ clk 1 mbx94h r/w - - vcc1 00h y 4 hmem 1 mbx95h r/w - - vcc1 07h 07h y 4 , 5 esmi source register 1 mbx96h r/w - - vcc2 00h y esmi mask 1 mbx97h r/w - - vcc2 00h y
245 total regs. mailbox index address system r/w 8051 addr. (7f00+) 8051 r/w power plane vcc 1 por vcc 2 por zero wait state (1) n o t e s register ir data register 1 mbx98h r/w - - vcc2 00h y force disk change register 1 mbx99h r/w - - vcc2 03h y floppy data rate select shadow register 1 mbx9ah r - - vcc2 n/a y uart1 fifo control shadow register 1 mbx9bh r - - vcc2 00h y uart2 fifo control shadow register 1 mbx9ch r - - vcc2 00h y fan control register 1 mbx9dh r/w 28h r/w vcc1 0x30 y mailbox register [10-1f] 16 mbx a0h-afh r/w 70h ? 7fh r/w vcc1 00h y 44 notes: 1. when accessed for a read or write by the system the registers marked with a ?y? will drive the zero wait state pin active. 2. interrupt is cleared when read by the 8051 3. interrupt is cleared when read by the host 4. when ireset_out is cleared (written from ?1? to?0?) 8051stp_clk bit d0 as well as hmem bits d1 and d0 are all set to ?1?. 5. these registers are reset 500us to 1ms following the condition that both vcc2 is valid and pwrgd is asserted given that the rtc is in normal mode and the vrt bit is set (refer to the rtc section). if the rtc is not in normal mode and/or the vrt bit is not set then these registers are reset within 10us following the condition that both vcc2 is valid and pwrgd is asserted.
246 mailbox registers interface base address logical device 9 in the FDC37N972 configuration space supports the mailbox registers interface. the three device configuration registers in ldn9 provide activation control and the base address for the mailbox registers interface run-time registers (table 163 ). register 0x30 is the activate register. the activation control (ldn9:cr30.0) qualifies address decoding for the mailbox registers interface; e.g., if the activate bit d0 in the activate register is ?0?, the mbx access port addresses will not be decoded; if the activate bit is ?1?, mbx access port addresses will be decoded depending on the values programmed in the mbx primary base address registers. registers 0x60 and 0x61 are the mbx primary base address registers. register 0x60 is the mbx primary base address high byte, register 0x61 is the mbx primary base address low byte. note: bit d0 in the mbx primary base address low byte must be ?0?. valid mailbox registers interface base address values are 0x0000 ? 0x0ffe. table 163 - mailbox registers interface configuration controls (ldn9) index type hard reset soft reset vcc2 por vcc1 & vcc0 por description d7 d6 d5 d4 d3 d2 d1 d0 0x30 r/w 0x00 0x00 0x00 - activate reserved act iva te 0x60 r/w 0x00 0x00 0x00 - mbx primary base address high byte ?0? ?0? ?0? ?0? a1 1 a1 0 a9 a8 0x61 r/w 0x00 0x00 0x00 - mbx primary base address low byte a7 a6 a5 a4 a3 a2 a1 ?0? mailbox registers interface access ports the mailbox registers access ports are runtime registers that occupy two addresses in the host i/o space (table 164 ). to access a mailbox register once the mailbox registers interface base address has been initialized, write the mailbox register index address to the mbx index port and read or write the mailbox register data from the mbx data port.
247 table 164 - mailbox registers interface access ports access port name host address host type power plane vcc2 por vcc1 por mbx index mbx base address r/w vcc2 0x00 - mbx data mbx base address + 1 r/w vcc2 - - mailbox registers there are 32 mailbox registers in the FDC37N972. the mbxa0?af and mbx84? 91 mailbox registers are general purpose registers. there are no interrupts for these registers. the system/8051 interface registers` mailbox register 0, system-to-8051, and mailbox register 1, 8051-to-system, are specifically designed to pass commands between the host and the 8051 (figure 35). if enabled, these registers can generate interrupts. mailbox register 0 and mailbox register 1 are not dual-ported, so the system bios and keyboard bios must be designed to properly share these registers. when the host performs a write of the system-to-8051 mailbox register, an 8051 int1 will be generated and seen by the 8051 if unmasked. when the 8051 writes to the system-to-8051 mailbox register, the data is blocked but the write forces the register to 0x00, providing a simple means for the 8051 to inform that host that an operation has been completed. when the 8051 writes the 8051-to-system mailbox register, an smi may be generated and seen by the host if unmasked. when the host cpu writes to the 8051-to-system mailbox register, the data is blocked but the write forces the 8051-to-system register to clear to zero, providing a simple means for the host to inform that 8051 that an operation has been completed. programmer?s note: the protocol used to pass commands back and forth through the mailbox registers interface is left to the system designer. smsc can provide an application example of working code in which the host uses the mailbox registers to gain access to all of the 8051 registers.
248 32 8-bit mail-box registers host cpu 8051 8051-to-system system-to-8051 smi int1 figure 35 - system-to-8051 mailbox interface registers block diagram mailbox register 0: system-to-8051 if enabled, an int1 will be generated when the system writes to mailbox register 0 (table 165 ). the interrupt source bit will be cleared when the 8051 reads this register. after reading mailbox register 0, the 8051 can clear the register to ?00h? by a dummy write to inform the host that the register contents have been read. table 165 - mailbox register 0 (system-to-8051) mailbox index 8051 address power plane default 0x82 0x7f08 vcc1 0x00 d7 d6 d5 d4 d3 d2 d1 d0 mbx type 1 rc rc rc rc rc rc rc rc 8051 type r/w r/w r/w r/w r/w r/w r/w r/w bit name d7 d6 d5 d4 d3 d2 d1 d0 note 1 rc = read-only register is cleared when written. mailbox register 1: 8051-to-system if enabled, an smi will be generated when the 8051 writes to mailbox register 1 (table 166 ). the smi interrupt will be cleared when the host reads this register.
249 after reading mailbox register 1, the system can clear the register to ?00h? by a dummy write to inform the 8051 that the register has been read. table 166 - mailbox register 1 (8051-to-system) mailbox index 8051 address power plane default 0x83 0x7f09 vcc1 0x00 d7 d6 d5 d4 d3 d2 d1 d0 mbx type 1 rc rc rc rc rc rc rc rc 8051 type r/w r/w r/w r/w r/w r/w r/w r/w bit name d7 d6 d5 d4 d3 d2 d1 d0 note 1 rc = read-only register is cleared when written. led controls the FDC37N972 has three independent led outputs that are programmable under 8051 control. led register host n/a 8051 0x7f21 power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 default 0 0 0 n/a 0 0 0 0 8051 access r/w r/w r/w r r/w r/w r/w r/w bit def fdd led enable fdd_ led1 fdd_ led0 status of pin mode pwr_ led1 pwr_ led0 bat_ led1 bat_ led0 note 1 00 fdd led is off 01 led flash; p=1.0 sec 10 led flash; p=0.5 sec 11 led is fully on 00 pwr led is off 01 led flash; p=3.0 sec 10 led flash; p=1.5 sec 11 led is fully on 00 battery led is off 01 led flash; p=1.0 sec 10 led flash; p=0.5 sec 11 led is fully on note 1: d7 =1; fdd_led pin is controlled by d6, d5, d7=0; fdd_led is controlled by the motor enable 0 pin from the fdc. when motor enable 0 pin is asserted the led is on. led on time is t=125msec; ?0? is on, ?1? is off. period ?p? is indicated above.
250 p t figure 36 - led output pulse width modulators overview in the FDC37N972 there are two independent programmable pulse-width modulated fan speed controllers. the FDC37N972 pwm fan speed controllers each include 11 fan speeds (f out ), 6-bit pulse-width resolution, and the ability to force the pwm outputs always high or low ( table 167 - fan speed control summary (stdby clock bit = ?0?) . note : each pwm fan speed controller in the FDC37N972 has two fan speeds, 7-bit pulse-width resolution, and can only force the pwm output always low (when dcc = 0). the FDC37N972 pwm fan speed controllers can be driven by the system clock when vcc2 is active, or by the 32.768khz standby clock (rtc) that is available when either vcc2 or vcc1 are active. programmer?s note: the availability of the 32khz standby clock is subject to the affects of the rtc clock control bits. the pwm fan speed control and fan control registers are accessible to both the host and the 8051 through the mailbox register interface (see mailbox register interface on page 249).
251 ta ble 167 - fan speed control summary (stdby clock bit = ?0?) fanx stdby clock bit 5 fanx clock control bit 1 fanx clock multi- plier bit 2 fanx clock select 1 bit 3 fanx clock select 0 bit 4 f out 6 (khz) 6-bit duty cycle control (dcc) duty cycle (%) 0 0 x x x 0 (low) 0 - 0 0 0 0 0 15.625 1-63 (dcc ? 64) 0 0 0 0 1 23.438 100 0 0 0 1 0 .040 0 0 0 1 1 .060 0 0 1 0 0 31.25 0 0 1 0 1 46.876 0 0 1 1 0 .080 0 0 1 1 1 .120 0 1 x x x 0 (high) - - ta ble 168 ? fan speed control summary (stdby clock bit = ?1?) fanx stdby clock bit 5 fanx clock control bit 1 fanx clock multi- plier bit 2 fanx clock select 1 bit 3 fanx clock select 0 bit 4 f out 6 (khz) 6-bit duty cycle control (dcc) duty cycle (%) 1 0 x x x 0 (low) 0 - 1 0 x 0 0 .032 1-63 (dcc ? 64) 1 0 x 0 1 .064 100 1 0 x 1 0 .128 1 0 x 1 1 reserved 1 1 x x x 0 (high) - - note 1 this is fan speed control register bit 0 note 2 this is fan control register bit 2 or bit 3 note 3 this is fan control regis ter bit 0 or bit 1 note 4 this is fan speed control register bit 7 note 5 this is fan control register bit 4 or bit 5 note 6 the f out frequency tolerance is 5% there are two fan speed control registers: pwm0 and pwm1. both of these registers are located in the FDC37N972 mailbox registers interface. pwm0 is mbx92 and pwm1 is mbx93 (see mailbox register interface on page 249). the fan speed control registers are in the FDC37N972 as shown in table 169 and table 170 .
252 the default values for both the pwm0 and the pwm1 registers are 0x00. these defaults take effect on vcc1 por. table 169 - fan 1 speed control register ( pwm0) mailbox index 8051 address power plane default 0x92 0x7f25 vcc1 0x00 d7 d6 d5 d4 d3 d2 d1 d0 mbx type r/w r/w r/w r/w r/w r/w r/w r/w 8051 type r/w r/w r/w r/w r/w r/w r/w r/w bit name fan clock select 0 duty cycle control fan clock control table 170 ? fan 2 speed control register (pwm1) mailbox index 8051 address power plane default 0x93 0x7f26 vcc1 0x00 d7 d6 d5 d4 d3 d2 d1 d0 mbx type r/w r/w r/w r/w r/w r/w r/w r/w 8051 type r/w r/w r/w r/w r/w r/w r/w r/w d7 d6 d5 d4 d3 d2 d1 d0 bit name fan clock select 0 duty cycle control fan clock control fan clock select 0, d7 the fan clock select 0 bit d7 in the fan speed control registers is used with the fan clock select 1 and the fan clock multiplier bits in the fan control register to determine the fan speed f out . note : there are separate pwm0 and pwm1 fan clock select 1 and fan clock multiplier bits in the fan control register (see section 0 fan control register). the affects of the fan clock select[1:0] bits are shown table 167 - fan speed control summary (stdby clock bit = ?0?) and in table 168 ? fan speed control summary (stdby clock bit = ?1?) . duty cycle control, d6 ? d1 the duty cycle control (dcc) bits determine the pwm fan duty cycle. the FDC37N972 has ? 1.56% duty cycle resolution. when dcc = ?000000? (min. value), f out is always low. when dcc is ?111111? (max. value), f out is almost always high; i.e., high for 63/64 th and low for 1/64 th of the f out period.
253 generally, the f out duty cycle (%) is (dcc ? 64) 100. fan clock control, d0 the fan clock control bit d0 is used to override the duty cycle control bits and force f out always high. when d0 = ?0?, the dcc bits determine the f out duty cycle. when d0 = 1, f out is always high, regardless of the state of the dcc bits. fan control register the fan control register contains fan clock select 1, fan clock multiplier, and standby clock control bits for each of the two fan speed controllers pwm0 and pwm1. the fan control register is mbx9d register (see mailbox registers interface (table 171 )). the default value for the fan control register is 0x30. the default value takes effect on vcc1 por. reserved bits in the fan control register cannot be written and return ?0? when read. table 171 - fan control register mailbox index 8051 address power plane default 0x9d 0x7f28 vcc1 0x30 d7 d6 d5 d4 d3 d2 d1 d0 mbx type r r r/w r/w r/w r/w r/w r/w 8051 type r r r/w r/w r/w r/w r/w r/w bit name reserved fan2 (pwm1) stdby clock 1 fan1 (pwm0) stdby clock 1 fan2 (pwm1) clock multi- plier fan1 (pwm0) clock multi- plier fan2 (pwm1) clock select 1 fan1 (pwm0) clock select 1 note 1 : the fanx stdby clock bits, d4 and d5, should not be switched when pwrgd is inactive; i.e., when vcc2 = 0v.
254 fan2 (pwm1) stdby clock, d5 the fan2 (pwm1) stdby clock bit d5 is used to determine the fan2 controller clock source. when the fan2 stdby clock bit = ?1?, the fan2 controller clock source is the 32.768khz rtc clock (vcc1/vcc2). the available fan2 f out frequencies when d5 = ?1? are shown in table 167 - fan speed control summary (stdby clock bit = ?0?) . when the fan2 stdby clock bit = ?0?, the fan2 controller clock source is the system clock (vcc2). the available fan2 f out frequencies when d5 = ?0? are shown in table 167 - fan speed control summary (stdby clock bit = ?0?) . the fan2 (pwm1) stdby clock bit default = ?1?. fan1 (pwm0) stdby clock, d4 the fan1 (pwm0) stdby clock bit d4 is used to determine the fan1 controller clock source. when the fan1 stdby clock bit = ?1?, the fan1 controller clock source is the 32.768khz rtc clock (vcc1/vcc2). the available fan1 f out frequencies when d4 = ?1? are shown in table 167 - fan speed control summary (stdby clock bit = ?0?) . when the fan1 stdby clock bit = ?0?, the fan1 controller clock source is the system clock (vcc2). the available fan1 f out frequencies when d4 = ?0? are shown in table 167 - fan speed control summary (stdby clock bit = ?0?) . the fan1 (pwm0) stdby clock bit default = ?1?. fan2 (pwm1) clock multiplier, d3 the fan2 clock multiplier bit d3 is used with the fan2 clock select 1 bit d1 and the pwm1 clock select 0 bit mbx93.7 to determine the fan2 f out when the fan2 stdby clock select bit is ?0?. when the fan2 clock multiplier bit = ?0?, no clock multiplier is used. when the fan2 clock multiplier bit = ?1?, the clock speed determined by the fan2 clock select [1:0] bits is doubled ( table 167 - fan speed control summary (stdby clock bit = ?0?) ). the fan2 clock multiplier bit does not affect the fan2 f out when the fan2 stdby clock select bit is ?1?. fan1 (pwm0) clock multiplier, d2 the fan1 clock multiplier bit d2 is used with the fan1 clock select 1 bit d0 and the pwm0 clock select 0 bit mbx92.7 to determine the fan1 f out when the fan1 stdby clock select bit is ?0?. when the fan1 clock multiplier bit = ?0?, no clock multiplier is used. when the fan1 clock multiplier bit = ?1?, the clock speed determined by the fan1 clock select [1:0] bits is doubled ( table 167 - fan speed control summary (stdby clock bit = ?0?) ). the fan1 clock multiplier bit does not affect the fan1 f out when the fan1 stdby clock select bit is ?1?. fan2 (pwm1) clock select 1, d1 the fan2 clock select 1 bit d1 is used with the fan2 clock multiplier bit d3 and the pwm1 clock select 0 bit mbx93.7 to determine the fan2 f out .
255 the affects of the fan clock select [1:0] bits are shown in table 167 - fan speed control summary (stdby clock bit = ?0?) and table 168 . fan1 (pwm0) clock select 1, d0 the fan1 clock select 1 bit d0 is used with the fan1 clock multiplier bit d2 and the pwm0 clock select 0 bit mbx92.7 to determine the fan1 f out . the affects of the fan clock select [1:0] bits are shown in table 167 - fan speed control summary (stdby clock bit = ?0?) and table 168 . esmi registers the host cam enable/disable the smi interrupts generated as a result of the 8051 writing to mailbox register 1. the host can read the esmi source register to determine fo the FDC37N972 mailbox interface was the cause of the smi. table 172 - esmi source register host address mbx96 8051 address n/a power vcc2 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 type r r r r r/w r/ r/ r/ bit name reserved res res res 8051_wr res res res 8051_wr this bit is set when a 8051-to-host mailbox has been written. this bit is cleared by a read of mailbox register 1 (mbx83.) table 173 - esmi mask register host address mbx97 8051 address n/a power vcc2 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 type r r r r r/w r r r/ bit name reserved res res res esmi_ mask reserved reserved reserved
256 esmi_mask setting this bit masks the 8051-to-host mailbox smi. 8051 controlled parallel port to facilitate activities such as reprogramming the flash memory without opening the unit, the 8051 is able to take control of the parallel port interface. the 8051 has three memory mapped registers that look like the host?s standard parallel port registers (status, control, and data) with one exception: the 8051?s parallel port status register contains a write bit (bit 0) that allows the 8051 to disconnect the interface from the host and take control. refer to the parallel port section for more information. sel 1 from/to host parallel port interface parallel port parallel port connector from/to 8051 parallel port interface pp_ha 1 0 figure 37 - parallel port multiplexor
257 operation registers the 8051 uses the following three memory mapped registers to gain access to and control the parallel port interface. parallel port status register host n/a 8051 0x7f3a power vcc2 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 8051 r/w r r r r r r r r/w system r/w n/a n/a n/a n/a n/a n/a n/a n/a bit def nbusy nack pe slct nerr 0 0 pp_ha 1 = host (or fdc) controls the parallel port interface. 0 = 8051 controls the parallel port interface (default). if 8051 access to the parallel port pins is enabled; the level of the parallel port status pins can be read by reading this register. bit d7 (nbusy): reflects the inverse state of pin busy bit d6 (nack): reflects the current state of pin nack bit d5 (pe): reflects the current state of pin pe bit d4 (slct): r epresents the current state of pin slct bit d3 (nerr): reflects the current state of pin nerr
258 parallel port control register host n/a 8051 0x7f3b power vcc2 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 8051 r/w r/w r/w r/w r/w r/w r/w r/w r/w system r/w n/a n/a n/a n/a n/a n/a n/a n/a bit def 0 0 pcd 0 slctin ninit alf strobe if 8051 access to the parallel port pins is enabled, the value of strobe, alf and slctin are inverted and output onto the parallel port control pins. the value of ninit is output onto the parallel port control pins. if pcd (parallel control direction) = 0, the data bus is output. if pcd = 1 the parallel port data bus is floating to allow read data in. parallel port data register host n/a 8051 0x7f3c power vcc2 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 8051 r/w r/w r/w r/w r/w r/w r/w r/w r/w system r/w n/a n/a n/a n/a n/a n/a n/a n/a bit def pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 if 8051 access to the parallel port pins is enabled; when read, this register reads the logic levels on the parallel port pins.
259 host controlled ir port it is possible to give direct control of the irrx and irtx pins to the host cpu by setting bit 2 of the multiplexing_1 register. the host communicates to the pins through its memory mapped ir data register shown here. ir data register host mbx 0x98 8051 n/a power vcc2 default 0x00 d7-d2 d1 d0 8051 r/w n/a n/a n/a system r/w r/w r r/w bit def reserved ir_rec ir_tx bit 1 and bit 0 are don?t care if bit 2 of the multiplexing_1 register is reset. (these bits are multiplexed onto the irtx and irrx pins when bit 2 of the multiplexing register is set). therefore, if the ir interface is on irrx (pin 21) and irtx (pin 20), then misc2 allows the ir interface to be switched between the ircc 2.0 block and the ir data register. note that misc7 allows the control of the com- rx/gpio8 (pin 141) and com-tx/gpio9 (pin 142) pins. if the com-rx and com-tx pins are used for ir, then this allows the ir interface access to be switched between the ircc 2.0 block and the 8051.
260 general purpose i/o (gpio) all general purpose registers are powered by vcc1. when gpio6, gpio10, out1, out5 - out9, gpio17, gpio20, gpio21, and kso12 are configured as alternate function outputs and pwrgd is inactive, i.e. vcc2 is 0v, these pins will tri-state to prevent back-biasing of external circuitry. gpio9 defaults to ?output?, ?low?, for both the default (gpio) function and the alternate (irtx) function, regardless of the state of pwrgd. this is done to prevent infrared transceiver damage the gpio defaults are shown in table 86 - 8051 on-chip external memory mapped registers on page 159. programmer?s note: the direction of alternate function pins that are multiplexed with general purpose i/o pins, i.e. where the gpio function is the default, is determined by the gpio direction bit. for example if the ks014 function of gpio4 is selected, bit 4 in gpio direction register a must be set to ?1?. this rule does not apply to default non-gpio pin functions that may have a gpio as an alternate function. gpio out reg bit output en alt func control bit alt func output out pin 1 0 nrd nwr figure 38 - output pin type
261 figure 39 - input pin type gpio out reg bit gpio in reg bit gpio dir bit alt func control bit alt func output gpio pin 1 0 alt func input nrd nwr figure 40 - gpio pin type in reg bit wake-up source bit nrd edge detector wake-up mask bit nwr wake-up irq in pin
262 memory mapped control registers gpio direction register a host n/a 8051 0x7f18 power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 bit def gpio7 1=output 0=input gpio6 1=out- put 0=input gpio5 1=out- put 0=input gpio4 1=out- put 0=input gpio3 1=out- put 0=input gpio2 1=out- put 0=input gpio1 1=out- put 0=input gpio0 1=out- put 0=input gpio input register a host n/a 8051 0x7f1a (r) power vcc1 default n/a d7 d6 d5 d4 d3 d2 d1 d0 bit des. status of pin gpio7 status of pin gpio6 status of pin gpio5 status of pin gpio4 status of pin gpio3 status of pin gpio2 status of pin gpio1 status of pin gpio0 gpio output register a host n/a 8051 0x7f19 power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 bit des. gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0
263 gpio direction register b host n/a 8051 0x7f1b power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 bit def. gpio15 1=out- put 0=input gpio14 1=out- put 0=input gpio13 1=out- put 0=input gpio12 1=out- put 0=input gpio11 1=out- put 0=input gpio10 1=out- put 0=input gpio9 1=out- put 0=input gpio8 1=out- put 0=input gpio output register b 1host n/a 8051 0x7f1c power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 bit def. gpio 15 gpio 14 gpio 13 gpio 12 gpio 11 gpio 10 gpio 9 gpio 8 gpio input register b host n/a 8051 0x7f1d (r) power vcc1 default n/a d7 d6 d5 d4 d3 d2 d1 d0 bit def. status of pin gpio15 status of pin gpio14 status of pin gpio13 status of pin gpio12 status of pin gpio11 status of pin gpio10 status of pin gpio9 status of pin gpio8
264 gpio direction register c host n/a 8051 0x7f1e power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 bit des. 0 0 gpio21 1=output 0=input gpio20 1=output 0=input gpio19 1=output 0=input gpio18 1=output 0=input gpio17 1=output 0=input gpio16 1=output 0=input gpio output register c host n/a 8051 0x7f1f power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 bit def. 0 0 gpio21 gpio20 gpio19 gpio18 gpio17 gpio16 gpio input register c host n/a 8051 0x7f20 (r) power vcc1 default n/a d7 d6 d5 d4 d3 d2 d1 d0 bit def. 0 0 status of pin gpio21 status of pin gpio20 status of pin gpio19 status of pin gpio18 status of pin gpio17 status of pin gpio16
265 out register d host n/a 8051 0x7f22 power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 bit def. out7 out6 out5 out4 out3 out2 out1 out0 out register e host n/a 8051 0x7f23 power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 bit def. 0 0 0 0 out11 out10 out9 out8 in register f host n/a 8051 0x7f24 (r) power vcc1 default n/a d7 d6 d5 d4 d3 d2 d1 d0 bit def. status of pin in7 status of pin in6 status of pin in5 status of pin in4 status of pin in3 status of pin in2 status of pin in1 status of pin in0
266 multifunction pin overview the FDC37N972 multifunction pins are mutliplexed on the following pins : 1. multiplexing is required for nirq8. 2. pwm0 and pwm1 have independent multiplex controls. 3. multiplexing is required for the flash rom address bit fa18. 4. multiplexing is required for the flash rom chip select nfcs. 5. multiplexing is required for the access.bus 2 interface pins ab2_data and ab2_clk. 6. out0 can be an open-drain or push-pull driver. refer to table 4 - alternate function pins on page 26 for a complete list of the FDC37N972 multifunction pins. the 8051 firmware, alone, controls the multiplexing functions for each of the multiplexed pins described in this section. multiplexing_1 register table 174 - multiplexing_1 register host address 8051 address power plane default - 0x7f3d vcc1 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 type r/w r/w r/w r/w r/w r/w r/w r/w bit name misc7 misc6 misc5 misc4 misc3 misc2 misc1 misc0 misc7 ? d7 the misc7 bit is used in the FDC37N972 to select the pin function and the buffer mode between gpio8 ? gpio9 and irrx and irtx table 175 .
267 table 175 - misc7 bit pin misc7 = 0 (default) misc7 = 1 gpio8 gpio8 ircc block com-rx port gpio9 gpio9 ircc block com-tx port misc6 ? d6 the misc6 bit is used in the FDC37N972 to select the pin function and the buffer mode between gpio17 and gatea20 ( table 176 ). table 176 - misc6 bit pin misc6 = 0 (default) misc6 = 1 gpio17 gpio17 gatea20 misc5 ? d5 the misc5 bit is used in the FDC37N972 to select the pin function and the buffer mode between out5 and out6 and the fdc floppy 1 drive controls nds1 and nmtr1 (table 177 ). table 177 - misc5 bit pin misc5 = 0 (default) misc5 = 1 out5 out5 nds1 out6 out6 nmtr1 misc4 ? d4 the misc4 bit is used in the FDC37N972 to select the pin function and the buffer mode between out10 and pwm0 for the out10 pin (table 178 ). note: this function only applies to the out10/pwm0 pin. the out11/pwm1 functions are selected by misc12 (multiplexing_2 register, below). note : the misc4 bit in the fdc37c95x applies to both out10/pwm0 and out11/pwm1. table 178 - misc4 bit misc4 description 0 out10 pin function selected ( default ) 1 pwm0 pin function selected misc3 ? d3 the misc3 bit, along with the misc1 bit, is used in the FDC37N972 to select the pin function and the buffer mode between gpio20 and gpio21, the 8051 uart rx and tx, and the ps/2 clk and data (table 179 ).
268 table 179 - misc3 and misc1 bits misc[3,1] pin gpio20 pin gpio21 [0,0] (default) gpio20 + 8051_rx * gpiio21 [0,1] ps2clk ps2dat [1,0] gpio20 + 8051_rx * 8051_tx ** [1,1] ps2clk ps2dat gpio20_dir bit should be set to 0 when operating as an 8051_rx pin. ** gpio21_dir bit must be set to 1 when operating as an 8051_tx pin. the ps/2 pins on gpio20 and gpio21 are disabled (internally pulled high) when the non-ps/2 alternate functions are selected. the ps/2 inputs under this condition are seen as a high to the ps/2 device interface logic. whenever a ps/2 channel is not enabled, the input signals to that channel must be high. the FDC37N972 provides this through the use of weak pull-ups since the em and kb channels share a common receive path and the im and ps2 channels also share a common receive path. 1 0 gpio20 gpio20_dir misc1 ps2_clk_out gpio20_out gpio20_in ps2_clk_in 8051_rx figure 41 - gpio20 alternate function structure
269 1 0 gpio21 misc1 misc3 8051_tx gpio21_out gpio21_in ps2_dat_in 0 1 ps2_dat_out gpio21_dir figure 42 - gpio21 alternate function structure misc2 ? d2 table 180 - misc2 bit pin misc2 = 0 (default) misc2 = 1 irtx from ircc block from ir data register irrx from ircc block from ir data register misc1 ? d1 see the description of the misc3 bit, above. note: the misc1 bit is not used with the misc0 bit in the FDC37N972. misc0 ? d0 the misc0 bit is used in the FDC37N972 to select the pin function and the buffer mode between out1 and nirq8 (table 181 ). table 181 - misc0 bit misc0 description 0 out1 pin function selected ( default ) 1 nirq8 pin function selected
270 multiplexing_2 register table 182 - multiplexing_2 register host address 8051 address power plane default - 0x7f40 vcc1 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 type r/w r/w r/w r/w r/w r/w r/w r/w bit name misc16 misc15 misc14 misc13 misc12 misc11 misc10 misc9 misc[16:15], d7 ? d6 the function of the gpio10 pin is reserved in the FDC37N972 when misc[16:15] = 1,1 (table 183 ). note: the FDC37N972 supports a single 16c550 uart interface. table 183 - mis c[16:15] bits multiplexing_2 register bits[7:6] selected pin function misc16 misc15 fdc37c95x FDC37N972 0 0 gpio10 (default) gpio10 (default) 0 1 ir_mode ir_mode 1 0 irrx3 irrx3 1 1 nrts2 reserved misc[14:13], d5 ? d4 the misc14 and misc13 bits are used in the FDC37N972 to select the pin function and the buffer mode between gpio6 and the ircc 2.0 irmode and irrx3 functions (table 184 ). table 184 - misc14 and misc13 bits misc[14:13] pin gpio6 [0:0] (default) gpio6 [0:1] ir_mode ( ircc 2.0 gp data ) output [1:0] irrx3 input [1:1] reserved
271 misc12 ? d3 the misc12 bit in the multiplexing_2 register is used in the FDC37N972 to select the pin function and buffer mode between out11 and pwm1 for the out11 pin (table 185 ). note: the misc12 bit in the fdc37c95x selects between gpio functions and serial port 2. the FDC37N972 supports a single 16c550 uart interface. table 185 - misc12 bit misc12 description 0 out11 pin function selected ( default ) 1 pwm1 pin function selected misc11 the misc11 bit is used in the FDC37N972 to select the pin function and the buffer mode between gpio19, out9 and dma channel 3 (table 186 ). table 186 - misc11 bit misc11 pin out9 pin gpio19 0 (default) out9 gpio19 1 drq3 ndack3 misc10 table 187 - misc10, misc17, and misc6 bits misc17 misc10 misc6 pin out8 pin kso12 0 0 0 out8 kso12 0 0 1 cpu_reset kso12 0 1 x drq2 kso12 1 0 0 out8 out8 1 0 1 cpu_reset cpu_reset 1 1 0 drq2 out8 1 1 1 drq2 cpu_reset with this definition, only the pair [out8 & cpu_reset] can not simultaneously exist on pins out8 and ks012.
272 1 0 out8 misc10 misc6 cpu_reset drq2 misc17 kso12 0 1 out8 1 0 kso12 figure 43 - out8 and kso12 alternate function operation misc9 table 188 - misc9 bi t misc9 pin gpio4 gpio5 0 (default) gpio4 gpio5 1 kso14 kso15 multiplexing_3 register table 189 - multiplexing_3 register host address 8051 address power plane default - 0x7f30 vcc1 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 type r/w r/w r/w r/w r/w r/w r/w r/w bit name misc23 misc22 misc21 misc20 misc19 misc18 misc17 misc8 misc23 ? d7 the buffer type for the gpio7 pin can be programmed as push-pull or open-drain. this makes gpio7 useful for other unique functions like nsci and extended keyboard scan controls like kso16. the
273 misc23 bit is used in the FDC37N972 to select the buffer mode for the gpio7 pin ( table 190 - misc23 bit ). table 190 - misc23 bit misc23 description 0 buffer mode for gpio7 is push-pull ( default ) 1 buffer mode for gpio7 is open-drain misc22 ? d6 the misc22 bit is used along with the misc5 bit in multiplexing_1 register to select the kbrst alternate function #2 of the out5 pin (table 191 - misc22 bit). table 191 - misc22 bit misc5 misc22 description 1 x nds1 pin function selected. 0 0 out5 pin function selected ( default ) 0 1 kbrst pin function selected misc21 ? d5 the misc21 bit is used in the FDC37N972 to select the buffer mode for the out0 pin (table 192 ). table 192 - misc21 bit misc21 description 0 buffer mode for out0 is open-drain ( default ) 1 buffer mode for out0 is push-pull misc20 ? d4 the misc20 bit in the multiplexing_3 register is used in the FDC37N972 to select the pin function and buffer mode between gpio and access.bus 2 functions for the gpio11 and gpio12 pins (table 193 ). table 193 - misc20 bit misc20 description 0 gpio pin functions selected ( default ) 1 access.bus 2 pin functions selected misc19 ? d3 the misc19 bit in the multiplexing_3 register is used in the FDC37N972 to select the pin function and buffer mode between nfcs and gpio0 for the nfcs pin (table 194 ).
274 table 194 - misc19 bit misc19 description 0 nfcs pin function selected ( default ) 1 gpio0 pin function selected misc18 ? d2 the misc18 bit in the multiplexing_3 register is used in the FDC37N972, along with bit d3 in the es mi mask register, to select the pin function and buffer mode for the out7 pin and the smi transfer mechanism to the host. (table 195 ). when misc18 = ?0?, the primary function of the out7 pin is selected and the smi is routed to the serial irq interface. if the smi is masked, sirq slot3 is available as irq2. when misc18 = ?1?, the alternate nsmi function of the out7 pin is selected, the pad is driven open- drain, and the serial irq slot3 is available as irq2. table 195 - misc18 and esmi mask bits esmi mask register 1 function d3 misc18 out7 pin sirq slot3 description 0 0 out7 nsmi serial smi ( default ) 0 1 nsmi irq2 parallel smi, serial irq irq2 available 1 0 out7 irq2 masked serial smi, irq2 available 1 1 nsmi irq2 parallel smi masked (inactive), irq2 available note 1 the esmi mask register is mbx97h (table 162 ). misc17 ? d1 table 196 - misc17 misc17 pin gpio18 pin kso13 0 gpio18 + ndack2 (1) kso13 1 ndack2 gpio18 note 1: ndack2 c an be received on the gpio18 pin when misc17 = 0 by setting the gpio18 direction bit to 0.
275 gpio18 misc17 gpio18_dir kso13 gpio18_out 1 0 kso13 ndack2 0 1 gpio18_in [ (misc17=0) | (gpio18_dir & misc17=1) ] figure 44 - gpio18 and kso13 alternate function operation misc8 ? d0 the misc8 bit in the multiplexing_3 register is used in the FDC37N972 to select the pin function and buffer mode between fa18 and gpio13 for the fa18 pin (table 197 ). note: the misc8 bit in the fdc37c95x selects between the gpio16 function and mid1. the FDC37N972 does not support the media id pins (see mid[1:0] fdd interface pins on page 37). table 197 - misc8 bit misc8 description 0 fa18 pin function selected ( default ) 1 gpio13 pin function selected misc8 pin gpio[16] 0 (default) gpio[16] 1 mid1 misc17 is described in the multiplexing_2 register section.
276 acpi pm1 block acpi pm1 block overview the FDC37N972 supports acpi as described in this section. these features comply with the acpi specification, revision 1.0, through a combination of hardware and 8051 software. the FDC37N972 implements the acpi fixed registers but includes only those bits that apply to the power button sleep button and rtc alarm events. the acpi wak_sts, slp_typx, and slp_en bits are also supported. the registers in the FDC37N972 acpi pm1 block occupy eight addresses in the host i/o space and are specified as offsets from the acpi pm1 block base address. the acpi pm1 block base address is relocatable depending on the values programmed in FDC37N972 configuration registers cr60 and cr61 in logical device number 1. the functions described in the following sub- sections can generate a sci event on the nec_sci pin. in the FDC37N972, an sci event is considered the same as an acpi wakeup or runtime event. the 8051 can also generate a sci on the nec_sci pin by setting the 8051_sci_sts bit in the 8051_pm_sts register (see nec_sci interface on page 287). acpi pm1 block sci event-generating functions power button with override the power button has a status and an enable bit in the pm1_blk of registers to provide an sci upon the button press. the status bit is software read/writeable by the 8051; the enable bit is read-only by the 8051. it also has a status and enable bit in the pm1_blk of registers to indicate and control the power button override (fail-safe) event. these bits are not required by acpi. the power button override event status bit is software read/writeable by the 8051; the enable bit is software read-only by the 8051. the enable bit for the override event is located at bit 1 in the pm1_cntrl2 register. the power button enable bit is set by the host to enable the generation of an sci due to the power button event. the status bit is set by the 8051 when it generates a power button event and is cleared by the host writing a ?1? to this bit (writing a ?0? has no effect); it can also be cleared by the 8051. if the enable bit is set, the 8051 will generate an sci power management event. sleep button the sleep button has a status and an enable bit in the pm1_blk of registers to provide an sci upon the button press. the status bit is software read/writeable by the 8051; the enable bit is read-only by the 8051. the sleep button enable bit is set by the host to enable the generation of an sci due to the sleep button event. the status bit is set by the 8051 when it generates a sleep button event and is cleared by the host writing a ?1? to this bit (writing a ?0? has no effect); it can also be cleared by the 8051. if the enable bit is set, the 8051 will generate an sci power management event. rtc alarm the acpi specification requires that the rtc alarm generate a hardware wake-up event from the sleeping state. the rtc alarm can be enabled as an sci event and its status can be determined through bits in the pm1_blk of registers. the status bit is software
277 read/writeable by the 8051; the enable bit is read-only by the 8051. the rtc enable bit is set by the host to enable the generation of an sci due to the rtc alarm event. the status bit is set by the 8051 when the rtc generates an alarm event and is cleared by the host writing a ?1? to this bit (writing a ?0? has no effect); it can also be cleared by the 8051. if the enable bit is set, the 8051 will generate an sci power management event. acpi pm1 block base address logical device 1 in the FDC37N972 configuration space supports the acpi pm1 block registers interface. three device configuration registers in ldn1 provide activation control and the base address programming for the acpi pm1 block registers (table 198 ). register 0x30 is the activate register. the activation control (ldn1:cr30.0) qualifies address decoding for the acpi pm1 block registers; e.g., if the activate bit d0 in the activate register is ?0?, the pm1 block addresses will not be decoded; if the activate bit is ?1?, pm1 block addresses will be decoded depending on the values programmed in the acpi pm1 block primary base address registers. registers 0x60 and 0x61 are the acpi pm1 block primary base address registers. register 0x60 is the acpi pm1 block primary base address high byte, register 0x61 is the acpi pm1 block primary base address low byte. note: the acpi pm1 block base address must be located on eight -byte boundaries; i.e., bits d0 ? d2 in the acpi pm1 block primary base address low byte must be ?0?. valid acpi pm1 block base address values are 0x0000 ? 0x0ff8. table 198 ? acpi pm1 bock configuration registers (ldn1) index type hard reset soft reset vcc2 por vcc1&vcc0 por description d7 d6 d5 d4 d3 d2 d1 d0 0x30 r/w 0x00 0x00 0x00 - activate reserved activate 0x60 r/w 0x00 0x00 0x00 - acpi pm1 block primary base address high byte ?0? ?0? ?0? ?0? a11 a10 a9 a8 0x61 r/w 0x00 0x00 0x00 - acpi pm1 block primary base address low byte a7 a6 a5 a4 a3 ?0? ?0? ?0?
278 acpi pm1 block description the acpi register model consists of a number of fixed register blocks that perform designated functions. a register block consists of a number of registers that perform status, enable and control functions. the acpi specification deals with events (which have an associated interrupt status and enable bits, and sometimes an associated control function) and control features. the status registers illustrate what defined function is requesting acpi interrupt services (sci). any status bit in the acpi specification has the following attributes: status bits are only set through some defined hardware or 8051 event. unless otherwise noted, status bits are cleared by the system writing a ?1? to that bit position, and upon vcc1 por. writing a ?0? has no effect. status bits only generate interrupts while their associated bit in the enable register is set. function bit positions in the status register have the same bit position in the enable register (there are exceptions to this rule, special status bits have no enables). note that this implies that if the respective enable bit is reset and the hardware event occurs, the respective status bit is set; however no interrupt is generated until the enable bit is set. this allows software to test the state of the event (by examining the status bit) without necessarily generating an interrupt. there are a special class of status bits that have no respective enable bit, these are called out specifically, and the respective enable bit in the enable register is marked as reserved for these special cases. the enable registers allow the setting of the status bit to generate an interrupt (under 8051 control). as a general rule there is an enable bit in the enable register for every status bit in the status register. the control register provides special controls for the associated event, or special control features that are not associated with an interrupt event. the order of a register block is the status registers, followed by enable registers, followed by control registers. registers the registers in the FDC37N972 acpi pm1 block occupy eight addresses in the host i/o space and are specified as offsets from the acpi pm1 block base address (table 199 ). the registers in the pm1 block are powered by vcc1.
279 table 199 - acpi pm1 block registers register size (bits) offset address pm1_sts 1 8 0 pm1_sts 2 8 1 +1h pm1_en 1 8 2 +2h pm1_en 2 8 3 +3h pm1_cntrl 1 8 4 +4h pm1_cntrl 2 8 5 +5h reserved 8 6 +6h reserved 8 7 +7h power management 1 status register 1 (pm1_sts 1 ) host register location: system i/o space 8051 register location: n/a default value: 00h on vcc1 por host attribute: read size: 8-bits bit name description 0-7 reserved reserved. these bits always return a value of zero. power management 1 status register 2 (pm1_sts 2) host register location: +1h system i/o space 8051 register location: 0x7f80 default value: 00h on vcc1 por host attribute: read/write (n ote 1) 8051 attribute read/write size: 8-bits note 1: these bits are set/cleared by the 8051 directly i.e., writing ?1? sets the bit and writing ?0? clears it. these bits can also be cleared by the host software writing a one to this bit position and by vcc1 por. writing a 0 by the host has no effect. an interrupt is generated to the 8051 when the host writes to this register. bit name description 0 pwrbtn_sts this bit can be set or cleared by the 8051 to simulate a power button status if the power is controlled by the 8051. the host writing a one to this bit can also clear this bit. the 8051 must generate the associated sci interrupt under software control.
280 bit name description 1 slpbtn_sts this bit can be set or cleared by the 8051 to simulate a sleep button status if the sleep state is controlled by the 8051. the host writing a one to this bit can also clear this bit. 2 rtc_sts this bit can be set or cleared by the 8051 to simulate a rtc status. the host writing a one to this bit can also clear this bit. 3 pwrbtnor_sts this bit can be set or cleared by the 8051 to simulate a power button override event status if the power is controlled by the 8051. the host writing a one to this bit can also clear this bit. 4-6 reserved reserved. these bits always return a value of zero. 7 wak_sts this bit can be set or cleared by the 8051. the host writing a one to this bit can also clear this bit. power management 1 enable register 1 (pm1_en 1) host register location: +2 system i/o space 8051 register location: n/a default value: 00h on vcc1 por host attribute: read size: 8-bits bit name description 0-7 reserved reserved. these bits always return a value of zero. power management 1 enable register 2 (pm1_en 2) host register location: +3 system i/o space 8051 register location: 0x7f81 default value: 00h on vcc1 por host attribute: read/write 8051 attribute: read size: 8-bits an interrupt is generated to the 8051 when the host writes this to register. bit name description 0 pwrbtn_en this bit can be read or written by the host. it can be read by the 8051 1 slpbtn_en this bit can be read or written by the host. it can be read by the 8051 2 rtc_en this bit can be read or written by the host. it can be read by the 8051 3-7 reserved reserved bits cannot be written and return ?0? when read.
281 power management 1 control register 1 (pm1_cntrl 1) host register location: +4 system i/o space 8051 register location: n/ a default value: 00h on vcc1 por host attribute: read size: 8-bits bit name description 0-7 reserved reserved bits cannot be written and return ?0? when read. power management 1 control register 2 (pm1_cntrl 2) host register location: +5 system i/o space 8051 register location: 0x7f82 default value: 00h on vcc1 por host attribute: read/write 8051 attribute: read. note: bit 5 is read/write size: 8-bits an interrupt is generated to the 8051 when the host writes to this register. bit name description 0 reserved reserved. this field always returns zero. 1 pwrbtnor_en this bit can be set or cleared by the host, read by the 8051 2-4 slp_typx these bits can be set or cleared by the host, read by the 8051 5 slp_en this bit is r/w by the host; reads by the host always return ?0?. this bit can be set (written as ?1?) but not cleared by the host (writing ?0? has no effect). this bit is r/w by the 8051, and reads by the 8051 return the true value of the bit. when set by the host, this bit is cleared by the 8051 writing a ?1? to it; writing ?0? has no effect. 6-7 reserved reserved bits cannot be written and return ?0? when read.
282 n ec_sci interface the nec_sci pin logic hardware is shown below in figure 42 . any or all of the pwrbtn_sts, slpbtn_sts, and rtc_sts bits in the pm1_sts 2 register can assert the nec_sci pin if enabled by the pwrbtn_en, slpbtn_en, and rtc_en bits in the pm1_en 2 register. see descriptions of these registers, above. the 8051_sci_sts bit can assert the nec_sci pin at any time, without being enabled. the 8051_sci_sts bit is located in the 8051_pm_sts register at mmcr address 0x7f83h (table 200 ). the 8051_sci_sts bit is in the FDC37N972 and is read/write by the 8051. if the 8051_sci_sts bit is ?1?, an interrupt is generated on the nec_sci pin. pm1_en 2 register pm1_sts 2 register pwrbtn_sts slpbtn_sts rtc_sts 8051_sci_sts 8051_pm_sts register nec_sci figure 45 - hardware nec_sci interface table 200 - 8051_pm_sts register host address 8051 address power plane default - 0x7f83 vcc1 0x00 d7 d6 d5 d4 d3 d2 d1 d0 host type - - - - - - - - 8051 type r r r r r r r r/w bit name reserved (reserved bits cannot be written and return ?0? when read) 8051_ sci_sts
283 real time clock general description the real time clock supercell (rtc) is a complete time of day clock with alarm, day of month alarm, one hundred year calendar, a century byte, and a programmable periodic interrupt. the rtc address space consists of two-128 bytes.banks of cmos ram (bank0 and bank1.) each bank is accessable via address and data ports. these access ports have relocatable addresses and are acessable by both the host and the 8051. each bank?s last addressable location accesses the shared rtc control. the remaining 127 bytes of bank0 contain the following: eleven registers of time, calendar, century, and alarm data, four control and status registers, and 111 bytes of general purpose registers. the remaining 127bytes of bank1 contain general purpose registers. features: allow 32khz clock input or a 32khz crystal. counts seconds, minutes, and hours of the day. counts days of the week, date, month and year. binary or bcd representation of time, calendar and alarm. 24 hour daily alarm. 30-day alarm. rtc/cmos bank addresses are relocatable. the rtc cmos bank0 index register (70h) is shadowed rtc interrupt (irq8) is available on the parallel nirq8 pin. rtc power source is switched internally between the vcc1 and vcc0 pins according to vcc1_pwrgd (see figure 4 - vcc2 power-up timing and figure 5 ? vcc1 pwrgd timing). lockable cmos ram address ranges (see table 223 - rtc, logical device 6 [logical device number = 0x06] configuration registers the rtc configuration registers, in logical device number 6, provide activation control and the base address for the run-time registers (see table 201 ) the activate bit register 0x30, bit d0 enables rtc/cmos bank0. the activate bit register 0x30, bit d1 enables rtc/cmos bank1.
284 t able 201 - rtc configuration registers description index type hard reset soft reset vcc2 por vcc1&v cc0 por d 7 d 6 d 5 d 4 d 3 d 2 d1 d0 0x30 r/w 0x00 0x00 0x00 - activate reserved activate cmos bank1 activate rtc/ cmos bank0 0x60 r/w 0x00 0x00 0x00 - rtc/cmos bank0 primary base address high byte ? 0 ? ? 0 ? ? 0 ? ? 0 ? a 1 1 a 1 0 a9 a8 0x61 r/w 0x70 0x70 0x70 - rtc/cmos bank0 primary base address low byte a 7 a 6 a 5 a 4 a 3 a 2 a1 ?0? 0x62 r/w 0x00 0x00 0x00 - cmos bank1 primary base address high byte ? 0 ? ? 0 ? ? 0 ? ? 0 ? a 1 1 a 1 0 a9 a8 0x63 r/w 0x74 0x74 0x74 - cmos bank1 primary base address low byte a 7 a 6 a 5 a 4 a 3 a 2 a1 ?0? 0xf1 r - - - - shadow rtc/cmos bank 0 index register isa host i/o interface each bank has a cmos address register and a cmos data register. each bank?s cmos address register is located at the corresponding base address setup by the configuration registers in table 201 . each bank?s cmos data register is located at an offest of the coresponding base (see table 202 .) bit d7 of both cmos address registers is not used for the cmos ram address decoding. all four cmos run time regesters are fully read/write. table 202 - cmos run time registers isa address* bank function bank0 * (r/w) rtc/cmos bank0 cmos address register bank0 * + 1(r/w) rtc/cmos bank0 cmos data register bank1 * (r/w) cmos bank1 cmos address register bank1 * + 2(r/w) cmos bank1 cmos data register
285 internal registers table 203 shows the address map of the rtc and cmos ram, eleven registers of time, calendar, century , and alarm data, four control and status registers , 239 bytes of cmos registers and one :shared rtc control register. each bank?s last addressable location accesses the same reigister: shared rtc control. table 203 - rtc and cmos ram address map bank base offest register type register function bank0 0 r/w register 0: seconds bank0 1 r/w register 1: seconds alarm bank0 2 r/w register 2: minutes bank0 3 r/w register 3: minutes alarm bank0 4 r/w register 4: hours bank0 5 r/w register 5: hours alarm bank0 6 r/w register 6: day of week bank0 7 r/w register 7: day of month bank0 8 r/w register 8: month bank0 9 r/w register 9: year bank0 a r/w register a: bank0 b r/w register b: (bit 0 is read only) bank0 c r register c: bank0 d r/w register d: day of month alarm bank0 32 r/w century byte bank0 e-31, 33-7f r/w general purpose bank0 7f r/w : shared rtc control bank1 0-7e r/w bank 1: general purpose bank1 7f r/w : shared rtc control all 256 bytes are directly writable and readable by the host with the following exceptions: registers c is read only bit 7 of register d is read only which can only be set by a read of register d. bit 6 of register d is read only . bit 7 of register a is read only bits 0 of register b is read only bits 7-1 of the shared rtc control register are read only
286 time calendar and alarm the processor program obtains time and calendar information by reading the appropriate locations. the program may initialize the time, calendar and alarm by writing to these locations. the contents of the twelve time, calendar and alarm registers can be in binary or bcd as shown in table 204 - rtc register valid range . before initializing the internal registers, the set bit in register b should be set to a "1" to prevent time/calendar updates from occurring. the program initializes the twelve locations in the binary or bcd format as defined by the dm bit in register b. the set bit may then be cleared to allow updates. the 12/24 bit in register b establishes whether the hour locations represent 1 to 12 or 0 to 23. the 12/24 bit cannot be changed without reinitializing the hour locations. when the 12 hour format is selected, the high order bit of the hours byte represents pm when it is a "1". once per second, the twelve time, calendar and alarm registers are updated, incrementing by one second and checking for an alarm condition. during the update cycle all the registers in table 204 , except register d, are not accessible by the processor program. the update cycle time is shown in table table 205 . the update logic contains circuitry for automatic end -of -month recognition as well as automatic leap year compensation. the three alarm registers may be used in two ways. first, when the program inserts an alarm time in the appropriate hours, minutes and seconds alarm locations, the alarm interrupt is initiated at the specified time each day if the alarm enable bit is high. the second usage is to insert a "don't care? state in one or more of three alarms registers. the "don't care" code is any hexadecimal byte from c0 to ff inclusive. that is the two most significant bits of each byte, when set to "1" create a "don't care" situation. an alarm interrupt each hour is created with a "don't care" code in the hours alarm location. similarly, an alarm is generated every minute with "don't care" codes in the hours and minutes alarm bytes. the "don't care" codes in all three alarm bytes create an interrupt every second. table 204 - rtc register valid range add register function bcd range binary range 0 register 0: seconds 00 -59 00 -3b 1 register 1: seconds alarm 00 -59 00 -3b 2 register 2: minutes 00 -59 00 -3b 3 register 3: minutes alarm 00 -59 00 -3b 4 register 4: hours 01 -12 am 01 -0c (12 hour mode) 81 -92 pm 81 -8c (24 hour mode) 00 -23 00 -17 5 register 5: hours alarm 01 -12 am 01 -0c (12 hour mode) 81 -92 pm 81 -8c (24 hour mode) 00 -23 00 -17 6 register 6: day of week 01 -07 01 -07 7 register 7: day of month 01 -31 01 -1f
287 add register function bcd range binary range 8 register 8: month 01 -12 01 -0c 9 register 9: year 00 -99 00 -63 d day of month alarm 01 -31 01 -1f 32 century byte 00 -99 00 -63 update cycle an update cycle is executed once per second if the set bit in register b is clear and the dv0 -dv2 divider is not clear. the set bit in the "1" state permits the program to initialize the time and calendar registers by stopping an existing update and preventing a new one from occurring. the primary function of the update cycle is to increment the seconds register, check for overflow, increment the minutes register when appropriate and so forth through to the year of the century byte. the update cycle also compares each alarm register with the corresponding time register and issues an alarm if a match or if a "don't care" code is present. the length of an update cycle is shown in table 205 . during the update cycle the time, calendar and alarm registers are not accessible by the processor program. if the processor reads these locations before the update cycle is complete the output will be undefined. the uip (update in progress) status bit is set during the interval. when the uip bit goes high, the update cycle will begin 244 m s later. therefore, if a low is read on the uip bit the user has at least 244 m s before time/calendar data will be changed. table 205 - rtc update cycle timing input clock frequency uip bit update cycle time minimum time before start of update cycle 32.768 khz 1 1948 m s - 32.768 khz 0 - 244 m s
288 control and status registers the rtc has four registers, which are accessible to the processor program at all times, even during the update cycle. register a b7 b6 b5 b4 b3 b2 b1 b0 uip dv2 dv1 dv0 rs3 rs2 rs1 rs0 uip the update in progress bit is a status flag that may be monitored by the program. when uip is a "1" the update cycle is in progress or will soon begin. when uip is a "0" the update cycle is not in progress and will not be for at least 244 m s. the time, calendar, and alarm information is fully available to the program when the uip bit is ?0?. the uip bit is a read only bit and is not affected by vcc1 por. writing the set bit in register b to a "1" inhibits any update cycle and then clears the uip status bit. dv2-0 three bits are used to permit the program to select various conditions of the 22 stage divider chain. table 206 shows the allowable combinations. the divider selection bits are also used to reset the divider chain. when the time/calendar is first initialized, the program may start the divider chain at the precise time stored in the registers. when the divider reset is removed the first update begins one -half second later. these three read/write bits are not affected by vcc1 por. table 206 - rtc divider selection bits oscillator register a bits frequency dv2 dv1 dv0 mode 0 0 0 oscillator disabled 32.768 khz 0 0 1 oscillator disabled 32.768 khz 0 1 0 normal operate 32.768 khz 0 1 1 test 32.768 khz 1 0 x test 1 1 x reset divider rs3-0 the four rate selection bits select one of 15 taps on the divider chain or disable the divider output. the selected tap determines rate or frequency of the periodic interrupt. the program may enable or disable the interrupt with the pie bit in register b. table 207 lists the periodic interrupt rates and equivalent output frequencies that may be chosen with the rs0 -rs3 bits. these four bits are read/write bits which are not affected by vcc1 por.
289 table 207 - rtc periodic interrupt rates rate select 32.768 khz time base rs3 rs2 rs1 rs0 period rate of interrupt frequency of interrupt 0 0 0 0 0.0 0 0 0 1 3.90625 ms 256 hz 0 0 1 0 7.8125 ms 128 hz 0 0 1 1 122.070 m s 8.192 hz 0 1 0 0 244.141 m s 4.096 khz 0 1 0 1 488.281 m s 2.048 khz 0 1 1 0 976.562 m s 1.024 khz 0 1 1 1 1.953125 ms 512 hz 1 0 0 0 3.90625 ms 256 hz 1 0 0 1 7.8125 ms 128 hz 1 0 1 0 15.625 ms 64 hz 1 0 1 1 31.25 ms 32 hz 1 1 0 0 62.5 ms 16 hz 1 1 0 1 125 ms 8 hz 1 1 1 0 250 ms 4 hz 1 1 1 1 500 ms 2 hz register b b7 b6 b5 b4 b3 b2 b1 b0 set pie aie uie res dm 24/12 dse set when the set bit is a "0", the update functions normally by advancing the counts once -per -second. when the set bit is a "1", an update cycle in progress is aborted and the program may initialize the time and calendar bytes without an update occurring in the middle of initialization. set is a read/write bit, which is not modified by vcc1 por or any internal functions. pie the periodic interrupt enable bit is a read/write bit which allows the periodic -interrupt flag (pf) bit in register c to cause the irqb port to be driven low. the program writes a "1" to the pie bit in order to receive periodic interrupts at the rate specified by the rs3 - rs0 bits in register a. a ?0? in pie blocks irqb from being initiated by a periodic interrupt, but the periodic flag (pf) is still set at the periodic rate. pie is not modified by any internal function, but is cleared to "0" by a vcc1 por.
290 aie the alarm interrupt enable bit is a read/write bit, which when set to a "1" permits the alarm flag (af) bit in register c to assert irqb. an alarm interrupt occurs for each second that the three time bytes equal the three alarm bytes (including a "don't care" alarm code of binary 11xxxxxx). when the aie bit is a "0", the af bit does not initiate an irqb signal. the vcc1 por port clears aie to "0". the aie bit is not affected by any internal functions. uie the update -ended interrupt enable bit is a read/write bit which enables the update -end flag (uf) bit in register c to assert irqb. the vcc1 por port or the set bit going high clears the uie bit. res reserved - read as zero dm the data mode bit indicates whether time and calendar updates are to use binary or bcd formats: the dm bit is written by the processor program and may be read by the program, but is not modified by any internal functions or by vcc1 por. a "1? in dm signifies binary data, while a "0" in dm specifies bcd data. 24/12 the 24/12 control bit establishes the format of the hours byte as either the 24 hour mode if set to a "1", or the 12 hour mode if cleared to a "0". this is a read/write bit that is not affected by vcc1 por or any internal function. dse the daylight savings enable bit is read only and is always set to a "0" to indicate that the daylight savings time option is not available. register c register c is a read only register b7 b6 b5 b4 b3 b2 b1 b0 irqf pf af uf 0 0 0 0
291 irqf the interrupt request flag is set to a "1" when one or more of the following are true: pf = pie = 1 af = aie = 1 uf = uie = 1 any time the irqf bit is a "1", the irqb signal is driven low. all flag bits are cleared after register c is read or by the vcc1 por port. pf the periodic interrupt flag is a read only bit which is set to a "1" when a particular edge is detected on the selected tap of the divider chain. the rs3 -rs0 bits establish the periodic rate. pf is set to a "1" independent of the state of the pie bit. pf being a "1" sets the irqf bit and initiates an irqb signal when pie is also a "1". the pf bit is cleared by vcc1 por or by a read of register c. af the alarm interrupt flag when set to a "1" indicates that the current time has matched the alarm time. a "1" in af causes a "1"to appear in irqf and the irqb port to go low when the aie bit is also a "1". a vcc1 por or a read of register c clears the af bit. uf the update -ended interrupt flag bit is set after each update cycle. when the uie bit is also a "1", the "1" in uf causes the irqf bit to be set and asserts irqb. a vcc1 por or a read of register c causes uf to be cleared. b3-0 the unused bits of register c are read as ?0? and cannot be written. register d msb lsb b7 b6 b5 b4 b3 b2 b1 b0 vrt 0 day of month vrt the valid ram and time (vrt) bit is cleared by the rtc to indicate that both the main power (vcc1) and the battery power (vcc0) are both low at the same time. this is the only case where the contents of the ram,as well as, the time and calendar registers are not valid. the vrt bit can only be set by a read of register d. the 8051 can set the vrt bit reading register d after both of the following condition are met: vcc1_pwrgd =1 and the 8051 completes initialization. the host can set the vrt bit reading register d after pwrgd =1 see section 0 power management. b6 read as zero and cannot be written. b5:b0 day of month alarm; these bits store the day of month alarm value. if set to 000000b, then a don?t care state is assumed. the host must configure the day of month alarm for these bits to do anything, yet they can be written at any time. if the day of month alarm is not enabled, these bits will return zeros. these bits are not affected by reset_drv, vcc1_por or vcc2_por. the bcd range for the day of
292 month of month alarm is 1-31 and the binary range is 01-1f. century byte the century byte is located at rtc/bank0 register 0x32. the century byte is incremented by one when the year byte changes from 99 or 0x63 to 0. the bcd range for the century byte is 00-99 and the binary range is 00-63. general purpose registers 0xeh-0x7eh, except 0x32 (the century byte) in bank0 and 0x0-0x7e in bank1 are general purpose "cmos" registers. these registers can be used by the host or 8051 and are fully available during the time update cycle. the contents of these registers are preserved by vcc0 power. registers eh-7eh are in bank0 and registers 80h-feh are in bank1. shared rtc control each bank?s last addressable location (0x7f) accesses the shared rtc control. the shared rtc control register implements an interface that allows the 8051 to read/write the rtc and cmos registers by use of the smart host protocol. refer to 8051 rtc cmos access section for the definition of this register. interrupts the rtc includes three separate fully automatic sources of interrupts to the processor. the alarm interrupt may be programmed to occur at rates from one -per -second to one -a -day. the periodic interrupt may be selected for rates from half -a -second to 122.070 m s. the update ended interrupt may be used to indicate to the program that an update cycle is completed. each of these independent interrupts are described in greater detail in other sections. the processor program selects which interrupts, if any, it wishes to receive by writing a "1" to the appropriate enable bits in register b. a "0" in an enable bit prohibits the irqb port from being asserted due to that interrupt cause. when an interrupt event occurs a flag bit is set to a "1" in register c, which are set independent of the state of the corresponding enable bits in register b. each of the three interrupt sources have separate flag bits in register c. the flag bits may be used with or without enabling the corresponding enable bits. the flag bits in register c are cleared (record of the interrupt event is erased) when register c is read. double latching is included in register c to ensure the bits that are set are stable throughout the read cycle. all bits which are high when read by the program are cleared, and new interrupts are held until after the read cycle. if an interrupt flag is already set when the interrupt becomes enabled, the irqb port is immediately activated, though the interrupt initiating the event may have occurred much earlier. when an interrupt flag bit is set and the corresponding interrupt -enable bit is also set, the irqb port is driven low. irqb is asserted as long as at least one of the three interrupt sources has its flag and enable bits both set. the irqf bit in register c is a "1" whenever the irqb port is being driven low. frequency divider the rtc has 22 binary divider stages following the clock input. the output of the divider is a 1- hertz signal to the update -cycle logic. the divider is controlled by the three divider bits (dv3 -dv0) in register a. as shown in table 206 the divider control bits can select the operating mode, or be used to hold the divider chain reset that allows precision setting of the time. when the divider chain is changed from reset to the operating mode, the first update cycle is one -half second later.
293 periodic interrupt selection the periodic interrupt allows the irqb port to be triggered from once every 500 ms to once every 122.07 m s. as table 207 shows, the periodic interrupt is selected with the rs0 -rs3 bits in register a. the periodic interrupt is enabled with the pie bit in register b. 8051 rtc cmos access the FDC37N972fr implements an interface that allows the 8051 to read/write the rtc and cmos registers under the following conditions: when nreset_out is active, or when vcc2 is off, or by use of the smart host protocol. rtccntrl (rtc control) register host n/a 8051 0x7ff5 power vcc1 default 0x80 the rtc control register is mirrored in cmos register 0x7fh in both bank0 and bank1. d7 d6 d5 d4 d3 d2 d1 d0 nsh 0 0 0 kreqh hreqh kreql hreql
294 nsh nsmart host - this bit is controlled by the 8051. when set to a ?1?, the host is not a smart host and does not recognize the sharing protocol. when set to a ?0?, the host is smart and can recognize the sharing protocol. when set to ?1?, this bit will clear hreqh and hreql. clearing this bit to ?0? will allow the 8051 to regain access to the cmos ram. kreql keyboard request low - the 8051 can set this bit when hreql is '0'. if the request is not granted, this bit is read back as a zero and the request must be tried again. note: after regaining control of the cmos, the 8051 must re-write the rtc low address register before accessing the rtc data register. this bit selects access to the cmos ram addresses 0-7f. hreql host request low - this bit can be set by the host when kreql is ?0?. if the request is not granted, this bit is read back as a ?0? and the request must be tried again. kreqh keyboard request high - this bit can be set by the 8051 when hreqh is ?0? if the request is not granted, this bit is read back as a ?0? and the request must be tried again. note: after regaining control of the cmos, the 8051 must re-write the rtc high address register before accessing the rtc data register. this bit selects access to the cmos ram addresses 80-ff. hreqh host request high - this bit can be set by the host when kreqh is ?0?. if the request is not granted, this bit is read back as a ?0? and the request must be tried again. nsh kreqx hreqx bus access 1 x x host 0 0 0 none 0 1 0 8051 0 0 1 host rtc address register (high and low) host n/a 8051 0x7ff8 & 0x7ff6 power vcc1 default 0x00 & 0x00 when kreq=1.in the rtc control register, the low address register and the high address register are used to access the 256 cmos ram registers. the low address register is used to provide the address to access the 128 cmos ram registers in bank0 and the high address register is used to provide the address to access the 128 cmos ram registers in bank1. bit d7 of the low address register and the high address register are not used for the address decode and are don?t care bits. rtc data register (high and low) host n/a 8051 0x7ff9 & 0x7ff7 power vcc1 default 0x00 & 0x00 the low register is used to access the first bank of 128 bytes, in cmos ram the high register is used to access the second bank of 128 registers. this register is used to read or write the selected cmos register when kreq=1.
295 32 k h z clock input the FDC37N972 uses the xosel pin to select either a 32.768khz input clock or a 32.768khz crystal to drive the real time clock interface ( table 2 - pin function description ). when xosel = ?0?, the rtc uses a 32.768khz crystal connected between the xtal1 and xtal2 pins. when xosel = ?1?, the rtc is driven by a 32.768khz single-ended clock source connected to the xtal2 pin. note: i cc0 3 10 m a for time-keeping operations under v cc0 using a single-ended clock source. i cc1 = 30 m a under v cc1 using a single-ended clock source. power management the rtc and cmos ram utilize vcc0 power plane (see figure 4 - vcc2 power-up timing and figure 5 - vcc1_pwrgd timing ) the vcc1 por does not affect the clock, calendar, or ram functions. when vcc1 por is active the following occurs: periodic interrupt enable (pie) is cleared to ?0?. alarm interrupt enable (aie) bit is cleared to ?0?. update ended interrupt enable (uie) bit is cleared to ?0?. update ended interrupt flag (uf) bit is cleared to ?0?. interrupt request status flag (irqf) bit is cleared to ?0?. periodic interrupt flag (pif) is cleared to ?0?. the rtc and cmos registers are not accessible. alarm interrupt flag (af) is cleared to ?0?. nirq pin is in high impedance state. if both the main power (vcc1) and the battery power (vcc0) are both low at the same time and then re-applied (ie. a new battery is installed) the following occurs: initialize all registers 00-0d to a ?00? when vcc1 is applied. the oscillator is disabled immediately. the vrt bit is cleared to ?0?. when pwrgd = 0, all host inputs are locked out so that the internal registers cannot be modified by the host system. the host lockout condition continues for 500usec (min) to 1msec (max) after pwrgd =1. the host lockout condition does not occur when either of the following occur: rtc divider selection mode is not in normal mode in table 206 . the vrt bit in register d is a "0". pci clock run support overview the FDC37N972 supports the pci nclkrun signal. nclkrun is used to indicate the pci clock status as well as to request that a stopped clock be started. see figure 46 for an example of a typical system implementation using nclkrun. nclkrun support is required because the FDC37N972 interrupt interface relies entirely on serial irqs. if an interrupt occurs while the pci clock is stopped, nclkrun must be asserted before the interrupt can be serviced. if the FDC37N972 serial irqs are disabled, nclkrun support is also disabled (see serirq mode bit function on page 303). the nclkrun pin is an open drain output and an input. refer to the pci mobile design guide rev 1.0 for a description of the nclkrun function. using nclkrun if nclkrun is sampled ?high?, the pci clock is stopped or
296 stopping. if nclkrun is sampled ?low?, the pci clock is starting or started (running). if a device in the FDC37N972 asserts or de- asserts an interrupt and nclkrun is sampled ?high?, the FDC37N972 can request the restoration of the clock by asserting the nclkrun signal asynchronously ( table 208 ). the FDC37N972 holds nclkrun low until it detects two rising edges of the clock. after the second clock edge, the FDC37N972 must disable the open drain driver (figure 47 ). the FDC37N972 must not assert nclkrun if it is already driven low by the central resource; i.e., the pci clock generator in figure 47 . the FDC37N972 will not assert nclkrun under any conditions if the serial irqs are disabled. the FDC37N972 must not assert nclkrun unless the line has been deasserted for two successive clocks; i.e., before the clock was stopped (figure 47 ). table 208 - FDC37N972 n clkrun function sirq_en internal interrupt request nclkrun action 0 x x none no change x none change 1 0 none 1 1 assert nclkrun note 1 ?change? means either-edge change on any or all parallel irqs routed to the serial irq block. the ?change? detection logic must run asynchronously to the pci clock and regardless of the serial irq mode; i.e., ?continuous? or ?quiet?. pci clock generator (central resource) master target FDC37N972 nclkrun pciclk figure 46 - nclkrun system implementation example
297 pci_clk nclkrun sirq_en any irq change 1 ,2 nclkrun driven by FDC37N972 FDC37N972 stops driving nclkrun 2 clks min. figure 47 - clock start illustration note 1 the signal ?any irq change? is the same as ?change? in table 208 . note 2 the FDC37N972 must continually monitor the s tate of nclkrun to maintain the pci clock until an active ?any irq change? condition has been transferred to the host in a serial irq cycle. for example, if ?any irq change? is asserted before nclkrun is de-asserted (not shown in figure 46 ), the FDC37N972 must assert nclkrun as needed until the serial irq cycle has completed.
298 serial interrupts msio will support the serial interrupt scheme, which is adopted by several companies, to transmit interrupt information to the system. the serial interrupt scheme adheres to the serial irq specification for pci systems version 6.0. timing diagrams for irqser cycle pciclk = 33 mhz_in pin irqser = sirq pin start frame timing with source sampled a low pulse on irq1. r t s r t s irqser pciclk host controller irq1 irq1 drive source r t none irq0 frame irq1 frame s r t irq2 frame none start start frame h sl or h 1 figure 48 - serial interrupts waveform "start frame" h=host control sl=slave control r=recovery t=turn-around s=sample start frame pulse can be 4-8 clocks wide. stop frame timing with host using 17 irqser sampling period s r t s irqser pciclk host controller irq15 driver r t none irq14 irq15 s r t iochck# none stop r t stop frame h i start next cycle 1 2 3 frame frame frame figure 49 - serial interrupt waveform "stop frame" h=host control r=recovery t=turn-around s=sample i= idle stop pulse is two clocks wide for quiet mode, three clocks wide for continuous mode. there may be none, one or more idle states during the stop frame.
299 the next irqser cycle?s start frame pulse may or may not start immediately after the turn-around clock of the stop frame. serirq mode bit function in the FDC37N972, the serirq_en (cr25.2) is used to enable the serial irq interface (table 209 ). the serirq_en bit is also used to enable pci clock run support (see section pci clock run supporton page 300). table 209 - serir q_en configuration control cr25 bit[2] name description 0 serirq_en serial irq disabled 1 serial irq enabled (default) irqser cycle control there are two modes of operation for the irqser start frame. quiet (active) mode any device may initiate a start frame by driving the irqser low for one clock, while the irqser is idle. after driving low for one clock the irqser must immediately be tri-stated without at any time driving high. a start frame may not be initiated while the irqser is active. the irqser is idle between stop and start frames. the irqser is active between start and stop frames. this mode of operation allows the irqser to be idle when there are no irq/data transitions which should be most of the time. once a start frame has been initiated the host controller will take over driving the irqser low in the next clock and will continue driving the irqser low for a programmable period of three to seven clocks. this makes a total low pulse width of four to eight clocks. finally, the host controller will drive the irqser back high for one clock then tri-state. any irqser device (i.e., the FDC37N972) which detects any transition on an irq/data line for which it is responsible must initiate a start frame in order to update the host controller unless the irqser is already in an irqser cycle and the irq/data transition can be delivered in that irqser cycle. continuous (idle) mode only the host controller can initiate a start frame to update irq/data line information. all other irqser agents become passive and may not initiate a start frame. irqser will be driven low for four to eight clocks by host controller. this mode has two functions. it can be used to stop or idle the irqser or the host controller can operate irqser in a continuous mode by initiating a start frame at the end of every stop frame. an irqser mode transition can only occur during the stop frame. upon reset, irqser bus is defaulted to continuous mode, therefore only the host controller can initiate the first start frame. slaves must continuously sample the stop frames pulse width to determine the next irqser cycle?s mode.
300 irqser data frame once a start frame has been initiated, the FDC37N972 will watch for the rising edge of the start pulse and start counting irq/data frames from there. each irq/data frame is three clocks: sample phase, recovery phase, and turn-around phase. during the sample phase, the FDC37N972 must drive the irqser (sirq pin) low, if and only if, its last detected irq/data value was low. if its detected irq/data value is high, irqser must be left tri-stated. during the recovery phase the FDC37N972 must drive the serirq high, if and only if, it had driven the irqser low during the previous sample phase. during the turn-around phase the FDC37N972 must tri-state the serirq. the FDC37N972 drives the irqser line low at the appropriate sample point if its associated irq/data line is low, regardless of which device initiated the start frame. the sample phase for each irq/data follows the low to high transition of the start frame pulse by a number of clocks equal to the irq/data frame times three, minus one e.g. the irq5 sample clock is the sixth irq/data frame, then the sample phase is {(6 x 3) - 1 = 17} the seventeenth clock after the rising edge of the start pulse.
301 table 210 ? irqser sampling periods irqser period signal sampled # of clocks past start 1 not used 2 2 irq1 5 3 nsmi/irq2 8 4 irq3 11 5 irq4 14 6 irq5 17 7 irq6 20 8 irq7 23 9 irq8 26 10 irq9 29 11 irq10 32 12 irq11 35 13 irq12 38 14 irq13 41 15 irq14 44 16 irq15 47 the sirq data frame will now support irq2 from a logical device; previously irqser period 3 was reserved for use by the system management interrupt (nsmi). when using period 3 for irq2 the user should mask off the FDC37N972 ?s smi via the esmi mask register. likewise, when using period 3 for nsmi, the user should not configure any logical devices as using irq2. irqser period 14 is used to transfer irq13. logical devices 0 (fdc), 3 (par port), 4 (ser port 1), 5 (ser port 2), 6 (rtc), and 7 (kbd) will have irq13 as a choice for their primary interrupt. stop cycle control once all irq/data frames have completed the host controller will terminate irqser activity by initiating a stop frame. only the host controller can initiate the stop frame. a stop frame is indicated when the irqser is low for two or three clocks. if the stop frame?s low time is two clocks then the next irqser cycle?s sampled mode is the quiet mode; and any irqser device may initiate a start frame in the second clock or more after the rising edge of the stop frame?s pulse. if the stop frame?s low time is three clocks, then the next irqser cycle?s sampled mode is the continuous mode, and only the host controller may initiate a start frame in the second clock or more after the rising edge of the stop frame?s pulse. latency latency for irq/data updates over the irqser bus in bridge-less systems with the minimum irq/data frames of seventeen will range up to 96 clocks (3.84 m s with a 25 mhz pci bus or 2.88 m s with a 33 mhz pci bus). if one or more pci to pci bridge is added to a system, the latency for irq/data updates from the secondary or tertiary buses will be a few clocks longer for synchronous buses, and approximately double for asynchronous buses.
302 eoi/isr read latency any serialized irq scheme has a potential implementation issue related to irq latency. irq latency could cause an eoi or isr read to precede an irq transition that it should have followed. this could cause a system fault. the host interrupt controller is responsible for ensuring that these latency issues are mitigated. the recommended solution is to delay eois and isr reads to the interrupt controller by the same amount as the irqser cycle latency in order to ensure that these events do not occur out of order. ac/dc specification issue all irqser agents must drive/sample irqser synchronously related to the rising edge of the pci bus clock. irqser (sirq) pin uses the electrical specification of the pci bus. electrical parameters will follow the pci specification section 4, sustained tri-state. reset and initialization the irqser bus uses npcirst as its reset signal (npcirst is equivalent to using nreset_out) and follows the pci bus reset mechanism. the irqser pin is tri-stated by all agents while npcirst is active. with reset, irqser slaves and bridges are put into the (continuous) idle mode. the host controller is responsible for starting the initial irqser cycle to collect system?s irq/data default values. the system then follows with the continuous/quiet mode protocol (stop frame pulse width) for subsequent irqser cycles. it is the host controller?s responsibility to provide the default values to the 8259?s and other system logic before the first irqser cycle is performed. for irqser system suspend, insertion, or removal application, the host controller should be programmed into continuous (idle) mode first. this is to guarantee irqser bus is in idle state before the system configuration changes. xnor-chain test mode an xnor-chain test structure is in to the FDC37N972 to allow users to confirm that all pins are in contact with the motherboard during assembly and test operations (figure 50 ). the xnor-chain test structure must be activated to perform these tests. when the xnor-chain is activated, the FDC37N972 pin functions are disconnected from the device pins, which all become input pins except for one output pin at the end of xnor-chain. the tests that are performed when the xnor- chain test structure is activated require the board-level test hardware to control the device pins and observe the results at the xnor-chain output pin. the xnor-chain test mode is activated and latched by: niow = nior = nmemwr = nmemrd = ?0? and xosel = vcc1_pwrgd = pwrgd = ?1? the xnor-chain test mode is deactivated by vcc1_por. all pins except for nreset_out, xosel, xtal1, xtal2, and vcc1_pwrgd are included as inputs to the xnor-chain test structure. the xnor-chain output pin is nreset_out.
303 i/o#1 i/o#2 i/o#3 i/o#n xnor out figure 50 - xnor-chain test structure FDC37N972 configuration overview the configuration of the FDC37N972 is very flexible and is based on the configuration architecture implemented in typical plug-and- play components. the FDC37N972 is designed for motherboard designs in which the resources required by their components are known. with its flexible resource allocation architecture, the FDC37N972 allows the bios to assign resources at post. configuration elements primary configuration address decoder the logical devices are configured through two configuration i/o ports (index and data). the bios uses these configuration ports to initialize the logical devices at post. the mode pin is a hardware configuration pin. the mode pin sets the configuration port?s default base address. note: all i/o addre sses are qualified with aen. configuration registers configuration register access primary configuration address decoder the logical devices are configured through two configuration access ports (index and data). the bios uses these ports to initialize the logical devices at post (table 211 ). the mode pin is a hardware configuration pin that sets the default configuration access port base address at power-up. the configuration ports base address can also be changed using the configuration ports base address register (see configuration registers base address registers (vcc2) on page 308). note: all i/o addresses are qualified with aen.
304 table 211 - FDC37N972 configuration access ports port name mode pin = 0 (10k pull-down resistor or tie to gnd) mode pin = 1 (10k pull-up resistor or tie to vcc1) type config port 0x03f0 (note 1) 0x0370 (note 1) write (nows isa i/o) index port 0x03f0 (note 1) 0x0370 (note 1) read/write (nows isa i/o) data port index port + 1 (note 1) read/write (nows isa i/o) the index and data ports are effective only when the chip is in the configuration state. note 1: this address can be changed by configuration registers 26h and 27h. entering the configuration state the device enters the configuration state when the following config key is successfully written to the config port. config key = < 0x55> exiting the configuration state the device exits the configuration state when the following config key is successfully written to the config port address. config key = < 0xaa> read accesing configuraton port the configuration port reads back a float condition when not in the configuration state. the configuration port reads back 0x00, after the configuration key 0x55 has been written to the configuration port, but prior any further writes to the configuration port. after the configuration index register has been written to at least once (in the configuration state,) then the last value written to the configuration index register (via the configuration port) can be read back. configuration registers base address registers (vcc2) the FDC37N972 configuration ports base address is relocatable beyond the two addressing options provided by the mode pin. registers cr26 and cr27 enable the relocatable configuration ports base address function. cr26 is the configuration ports base address least significant byte; cr27 is the most significant byte (table 212 ). the configuration ports base address is relocatable on even-byte boundaries; i.e., a0 = ?0?. valid configuration ports base address values are 0x0000 ? 0x0ffe. at power-up, the configuration ports base address is determined by the mode pin. to relocate the configuration ports base address after power-up, first write the lower address byte (lsb) of the new base address to cr26 and then write the upper address bits to cr27. note: writing cr27 changes the configuration ports base address. the ability to relocate the configuration ports base address can prevent address conflicts, particularly when tape drives are used.
305 table 212 - configuration port address registers description index type hard reset & vcc2 por 1 soft reset, vcc1 por & vcc0 por register name d7 d6 d5 d4 d3 d2 d1 d0 global configuration registers 0x26 2 r/w mode = 0: 0xf0 mode = 1: 0x70 - configuration port base address byte 0 (lsb) a7 a6 a5 a4 a3 a2 a1 ?0? 0x27 3 r/w mode = 0: 0x03 mode = 1: 0x03 - configuration port base address byte 1 (msb) ?0? ?0? ?0? ?0? a11 a10 a9 a8 note 1 the mode pin determines the configuration port base address following hard reset and vcc2 por. note 2 the configuration ports base address is relocatable on even-byte boundaries; i.e., a0 = ?0?. note 3 writing cr27 changes the configuration ports base address. the FDC37N972 configuration register map is shown below in table 213 . configuration register reset conditions hard reset = vcc2 por or reset_out pin asserted. soft reset = configuration control register bit0 set to a one by host.
306 table 213 - FDC37N972 configuration register map index type hard reset soft reset configuration register name global configuration registers 0x02 w 0x00 0x00 config control 0x03 - - - reserved 0x07 r/w 0x00 0x00 logical device number 0x17 - - - reserved 0x20 r 0x0a 0x0a fdc37n971 0x0b 0x0b FDC37N972 0x21 r 0x00 0x00 device rev - hard wired 0x22 r/w 0x00 n/a power control 0x23 r/w 0x00 n/a power mgmt 0x24 r/w 0x04 n/a osc 0x25 r/w 0x04 n/a devicemode 0x26 r/w see above configuration port base address (lsb) 0x27 r/w see above configuration port base address (msb) 0x28 ? 0x2f - 0x00 0x00 reserved (test mode registers) logical device 0 configuration registers (fdc) 0x30 r/w 0x00 0x00 activate 0x60, 0x61 r/w 0x03, 0xf0 0x03, 0xf0 primary base i/o address 0x70 r/w 0x06 0x06 primary interrupt select 0x74 r/w 0x02 0x02 dma channel select 0xf0 r/w 0x0e n/a fdd mode register 0xf1 r/w 0x00 n/a fdd option register 0xf2 r/w 0xff n/a fdd type register 0xf4 r/w 0x00 n/a fdd0 0xf5 r/w 0x00 n/a fdd1 logical device 1 configuration registers (pm1) 0x30 r/w 0x00 0x00 activate 0x60, 0x61 r/w 0x00, 0x00 0x00, 0x00 primary base i/o address logical device 2 configuration registers (reserved) logical device 3 configuration registers (parallel port) 0x30 r/w 0x00 0x00 activate 0x60, 0x61 r/w 0x00, 0x00 0x00, 0x00 primary base i/o address 0x70 r/w 0x00 0x00 primary interrupt select 0x74 r/w 0x04 0x04 dma channel select 0xf0 r/w 0x3c n/a parallel port mode register 0xf1 r/w 0x00 n/a parallel port cnfgb shadow register
307 index type hard reset soft reset configuration register name logical device 4 configuration registers (serial port 1) 0x30 r/w 0x00 0x00 activate 0x60, 0x61 r/w 0x00, 0x00 0x00, 0x00 uart register base i/o address 0x70 r/w 0x00 0x00 primary interrupt select 0xf0 r/w 0x00 n/a serial port 1 mode register logical device 5 configuration registers (infrared) 0x30 r/w 0x00 0x00 activate 0x60, 0x61 r/w 0x00, 0x00 0x00, 0x00 primary base i/o address 0x62, 0x63 r/w 0x00, 0x00 0x00, 0x00 sce register base i/o address 0x70 r/w 0x00 0x00 primary interrupt select 0x74 r/w 0x04 0x04 ircc 2.0 dma channel select 0xf0 r/w 0x00 n/a mode register 0xf1 r/w 0x02 n/a ir options register 0xf2 r/w 0x03 n/a ir half duplex timeout 0xf7 r/w 0x00 0x00 software select a 0xf8 r/w 0x00 0x00 software select b logical device 7 configuration registers (rtc) 0x30 r/w 0x00 0x00 activate 0x60, 0x61 r/w 0x00, 0x70 0x00, 0x70 rtc bank 0 primary base address 0x62, 0x63 r/w 0x00, 0x74 0x00, 0x74 rtc bank 1 primary base address 0x70 r/w 0x00 0x00 primary interrupt select 0xf0 r/w 0x00 n/a real time clock mode register 00xf1 r - - shadowed rtc/cmos bank 0 index register logical device 7 configuration registers (kbd) 0x30 r/w 0x00 0x00 activate 0x70 r/w 0x00 0x00 primary interrupt select 0x72 r/w 0x00 0x00 second interrupt select 0xf0 r/w 0x00 0x00 krst_ga20 logical device 8 configuration registers (ec) 0x30 r/w 0x00 0x00 activate 0x60, 0x61 r/w 0x00, 0x62 0x00, 0x62 eci register base i/o address logical device 9 configuration registers (mailbox) 0x30 r/w 0x00 0x00 activate 0x60, 0x61 r/w 0x00, 0x00 0x00, 0x00 mailbox register base i/o address
308 chip level (global) control/configuration registers [0x00-0x2f] the chip-level (global) registers lie in the address range [0x00-0x2f]. the index port is used to select a configuration register in the chip. the data port is then used to access the selected register. these registers are accessible only in the configuration state. table 214 - global configuration registers register address description state chip (global) control registers 0x00 - 0x01 reserved, writes are ignored, reads return 0. config control 0x02 w the hardware automatically clears this bit after the write; there is no need for software to clear the bits. bit [0] = 1: soft reset; refer to table 213 for the soft reset value for each register. c card level reserved 0x03w reserved - writes are ignored, reads return 0. 0x04 - 0x06 reserved - writes are ignored, reads return 0. logical device # 0x07 r/w a write to this register selects the current logical device. this allows access to the control and configuration registers for each logical device. note: the activate command operates only on the selected logical device. c card level reserved 0x08 - 0x1f reserved - writes are ignored, reads return 0. chip-level, smsc defined device id hard wired 0x20 r a read-only register which provides device identification. bit[7-0] fdc37n971 = 0x0a FDC37N972 = 0x0b c device rev hard wired 0x21 r a read-only register which provides device revision information. bits[7-0] = 0x00 when read c
309 register address description state powercontrol 0x22 r/w bit[0] fdc power bit[1:2] reserved (read as 0) bit[3] parallel port power bit[4] serial port 1 power bit[5] serial port 2 power bit[6:7] reserved (read as 0) =0 power off or disabled =1 power on or enabled c power mgmt 0x23 r/w bit[0] fdc bit[1:2] reserved (read as 0) bit[3] parallel port bit[4] serial port 1 bit[5] serial port 2 bit[6:7] reserved (read as 0) =0 power off or disabled =1 power on or enabled c osc 0x24 r/w bit[1:0] reserved, set to ?0? bit[3:2] osc =01 osc is on, brg clock is on when pwrgd is active, osc is off and brg clock is disabled (default) =10 same as above (01) case =00 osc is on, brg clock enabled =11 osc is off, brg clock is disabled bit[6:4] clk_out select =[0,0,0] clk_out = 1.8432 mhz =[0,0,1] clk_out = 14.318 mhz =[0,1,0] clk_out = 16 mhz =[0,1,1] clk_out = 24 mhz =[1,0,0] clk_out = 48 mhz =[1,0,1] reserved =[1,1,x] reserved bit[7] nirq8 polarity =0 nirq8 is active high =1 nirq8 is active low note: this polarity bit not only affects the nirq8 pin, but is also reflected in the serial irq sample phase for the irq8 frame for the serial irq bus. c
310 register address description state device mode 0x25 r/w bit [1-0] flash timing this register is used to program the width of flash read (nfrd) and flash write (nfwr) signals during host flash accesses. = 0,0 : nfrd/nfwr width = 3 sclks = 0,1 : width = 2.5 sclks = 1,0 : width = 2 sclks = 1,1 : reserved, do not use. bit[2] serirq mode = 0 : serial irq disabled. = 1 : serial irq enabled (default). bit [4:3] parallel port fdc = [0:0] normal = [0:1] ppfd1 mode = [1:0] ppfd2 mode = [1:1] reserved bit [7:5] reserved - writes ignored, reads return ?0?. chip level vendor defined 0x26 reserved - writes are ignored, reads return 0. test registers 0x27-0x2b smsc test mode registers, reserved for smsc. test 0 0x2c test modes - reserved for smsc. users should not write to this register, may produce undesired results. test 1 0x2d r/w test modes : reserved for smsc. users should not write to this register; may produce undesired results. c test 2 0x2e r/w test modes - reserved for smsc. users should not write to this register; may produce undesired results. c test 3 0x2f r/w test modes - reserved for smsc. users should not write to this register; may produce undesired results. c
311 logical device configuration/control registers [0x30-0xff] used to access the registers that are assigned to each logical unit. this chip supports six logical units and has six sets of logical device registers. the logical devices are floppy, parallel, serial 1 and ircc 2.0 (uart), real time clock, and keyboard controller. a separate set (bank) of control and configuration registers exists for each logical device and is selected with the logical device # register (0x07). the index port is used to select a specific logical device register. these registers are then accessed through the data port. the logical device registers are accessible only when the device is in the configuration state the logical register addresses are listed in table 215 . table 215 - logical device configuration registers logical device register address description state activate (1) (0x30) bits[7:1] reserved, set to ?0?. bit[0] = 1 activates the logical device currently selected through the logical device # register. = 0 logical device currently selected is inactive. c bank activation for rtc only (0x30) for rtc only bits[7:2] reserved, set to ?0?. bit[1] activates bank 1 bit[0] activates bank 0 bit[1:0] = 1 activates the logical device currently selected through the logical device # register. = 0 logical device currently selected is inactive. logical device control (0x31-0x37) reserved - writes are ignored, reads return ?0?. c logical device control (0x38-0x3f) vendor defined ? reserved - writes are ignored, reads return ?0?. c memory base address (0x40-0x5f) reserved - writes are ignored, reads return ?0?. c i/o base address (see table 216 ) (0x60-0x6f) 0x60 = addr[15:8] 0x61= addr[7:0] all logical devices contain 0x60, 0x61. unused registers will ignore writes and return ?0? when read. c
312 logical device register address description state interrupt select (0x70,072) 0x70 is implemented for each logical device. refer to interrupt configuration register description. only the kybd controller uses interrupt select register 0x72. unused register (0x72) will ignore writes and return ?0? when read. interrupts default to edge high (isa compatible). c (0x71,0x73) reserved - not implemented. these register locations ignore writes and return ?0? when read. dma channel select (0x74) only 0x74 is implemented for fdc , and parallel port. refer table 218 - dma channel select configuration registers . c (0x75) reserved - not implemented and ignores writes and returns ?0? when read. 32-bit memory space configuration (0x76-0xa8) reserved - not implemented. these register locations ignore writes and return ?0? when read. logical device (0xa9-0xdf) reserved - not implemented. these register locations ignore writes and return ?0? when read. c logical device configuration (0xe0-0xfe) reserved - vendor defined (see smsc defined logical device configuration registers). c reserved 0xff reserved c note1: a logical device will be active and powered up according to the following equation:device on (active) = (activate bit set and pwr/control bit set) and (8051 disable bit set) the logical device's activate bit and its pwr/control bit are linked such that setting or clearing one sets or clears the other. three bits in the 8051?s disable register (see keyboard spec), bits d7, d6 and d4 are capable of overriding the activate and pwr/control bit settings for logical devices 3, 4 and 0 respectivelely. thus clearing bit d7 of the disable register will disable the fdc regardless of the fdc?s activate and pwr/control bits. when d7 of the disable register is set, the fdc?s activate and pwr/control bits will determine the on/off state of the fdc. if the i/o base addr of the logical device is not within the base i/o range as shown in the logical device i/o map, then read or write is not valid and is ignored.
313 i/o base address configuration register description table 216 - logical device, base i/o addresses logical device number logical device register index base i/o range (note 1) fixed base offsets 0x00 fdc 0x60,0x61 [0x100:0x0ff8] on 8 byte boundaries +0 : sra +1 : srb +2 : dor +3 : tsr +4 : msr/dsr +5 : fifo +7 : dir/ccr 0x01 reserved 0x02 reserved 0x03 parallel port 0x60,0x61 [0x100:0x0ffc] on 4 byte boundaries (epp not supported) or [0x100:0x0ff8] on 8 byte boundaries (all modes supported, epp is only available when the base address is on an 8- byte boundary) +0 : data | ecpafifo +1 : status +2 : control +3 : epp address * +4 : epp data 0 * +5 : epp data 1 * +6 : epp data 2 * +7 : epp data 3 * +400h : cfifo | ecpdfifo | tfifo | cnfga +401h : cnfgb +402h : ecr 0x04 serial port 1 0x60,0x61 [0x100:0x0ff8] on 8 byte boundaries +0 : rb/tb | lsb div +1 : ier | msb div +2 : iir/fcr +3 : lcr +4 : mcr +5 : lsr +6 : msr +7 : scr 0x05 ircc 2.0 (uart) 0x60,0x61 [0x100:0x0ff8] on 8 byte boundaries +0 : rb/tb | lsb div +1 : ier | msb div +2 : iir/fcr +3 : lcr +4 : mcr +5 : lsr +6 : msr +7 : scr
314 logical device number logical device register index base i/o range (note 1) fixed base offsets 0x05 ircc 2.0 (ir-sce) 0x62, 0x63 [0x100:0x0ff8] on 8 byte boundaries +0 : register block n, address 0 +1 : register block n, address 1 +2 : register block n, address 2 +3 : register block n, address 3 +4 : register block n, address 4 +5 : register block n, address 5 +6 : register block n, address 6 +7: sce master control reg. 0x06 rtc 0x60, 0x61 0x62, 0x63 [0x00:0x0ffe] [0x00:0x0ffd] bank 0 base address +0 : address register +1 : data register * bank 1 base address +0 : address register +2 : data register * 0x07 kybd n/a not relocatable fixed base address 0x60 : data register 0x64 : command/status reg. 0x08 eci 0x60, 0x61 2 [0x0000:0xffa] relocatable +0 : data register 3 +4 : c ommand r egister 0x09 mailbox register 0x60, 0x61 [0x0000:0x0ffe] +0 : index +1 : data note 1: this chip uses all isa address bits to decode the base address of each of its logical devices. note 2: please refer to table 49 for further description. note 3: please refer to table 50 for further description. note*: when these registers are accessed the nnows line is not asserted. all other registers in this table assert the nnows signal when accessed.
315 interrupt select configuration register description table 217 - interrupt select configuration registers name reg index definition state interrupt request level select 0 0x70 (r/w) bit [3-0] select which interrupt level is used for interrupt 0. 0x00=no interrupt selected. 0x01=irq1 0x02=irq2 0x0e= irq14 0x0f= irq15 all pin-type interrupts are edge high (except ecp/epp). each logical device?s interrupts selected through this register physically select the interrupts to be used by the FDC37N972 for either the serial irq interface or for the individual pin-type isa interrupts if selected. setting the irq through this register for the parallel port is not reflected in the enhanced parallel port cnfgb register, software must set the dma/irq bits in the parallel port logical device config register 0xf1 (parallel port cnfgb shadow register). c note : an interrupt is activated by setting the interrupt request level select 0 register to a non-zero value and : 1. for the fdc logical device by setting dmaen, bit d3 of the digital output register. 2. for the pp logical device by setting irqe, bit d4 of the control port and in addition 3. for the pp logical device in ecp mode by clearing serviceintr, bit d2 of the ecr. 4. for the serial port logical device by setting any combination of bits d0-d3 in the ier and by setting the out2 bit in the uart's modem control (mcr) register. 5. for the rtc by (refer to the rtc section of this specification). 6. for the kybd by (refer to the kybd controller section of this specification).
316 dma channel select configuration register description table 218 - dma channel select configuration registers name reg index definition state dma channel select 0 0x74 (r/w) bit [2:0] select the dma channel. 0x00=dma0 0x01=dma1 0x02=dma2 0x03=dma3 0x04-0x07= no dma active c note: a dma channel is activated by setting the dma channel select 0 register to [0x00-0x03] and : 1. for the fdc logical device by setting dmaen, bit d3 of the digital output register 2. for the pp logical device in ecp mode by setting dmaen, bit d3 of the ecr 3. for the uart2 logical device, by setting the dma enable bit. refer to the ircc 2.0 specification available from smsc note: dmareq pins must tri-state if not used/selected by any logical d evice.
317 irq and dma enable and disable any time the irq and/or dma channels for a logical device are disabled by a register in that logical device, the irq and/or ndack must be disabled. this is in addition to the irq and ndack disabled by the configuration registers (activate bit cleared or address outside of valid range or the interrupt select register set to 0x00 or the dma channel select register set to 0x04). logical device 0 (fdc) for the following cases, the irq and dack used by the fdc are disabled (high impedance), i.e., will not respond to the dreq digital output register (base+2) bit d3 (dmaen) set to "0". the fdc is in power down (disabled). logical device 5 (serial port1) modem control register (mcr) bit d2 (out2) - when out2 is a logic "0", then the serial port interrupt is forced to a high impedance state - disabled. logical device 5 (serial port2/usart) interrupt is disabled when: modem control register (mcr) bit 2 (out2) - when out2 is a logic ?0?, then logical device 5?s interrupt is forced to a high impedance state, i.e., disabled. this applies to all uart/ir modes of operation. drq is disabled when: sce configuration register b bit-0 (dma enable) - when the dma enable bit is a logic ?0?, then logical device 5?s drq pin is forced to a high impedance state, i.e., disabled. when the dma enable bit is set to logic ?1?, then logical device 5?s drq pin is active and drives low until the device issues a dma request at which point the drq pin drives high. this eliminates the need for an external pull-down resistor on the logical device 5?s drq pin. parallel port spp and epp modes: control port (base+2) bit d4 (irqe) set to "0", irq is disabled (high impedance). ecp mode: (dma) dmaen from ecr register. irq - see table below. mode (from ecr register) irq pin controlled by pdreq pin controlled by 000 printer irqe dmaen 001 spp irqe dmaen 010 fifo (on) dmaen 011 ecp (on) dmaen 100 epp irqe dmaen 101 res irqe dmaen 110 test (on) dmaen 111 config irqe dmaen
318 real time clock (rtc) (refer to the rtc section) keyboard controller (kybd) (refer to the keyboard controller section) smsc defined logical device configuration registers the smsc specific logical device configuration registers reset to their default values only on hard resets generated by vcc2 por or the nreset_out signal. these registers are not effected by soft resets.
319 table 219 - fdc, logical device 0 [logical device number = 0x00] name reg index definition state fdd mode register default = 0x0e 0xf0 r/w bit[0] floppy mode =0 normal floppy mode (default) =1 enhanced floppy mode 2 (os2) bit[1] fdc dma mode =0 burst mode is enabled =1 non-burst mode (default) bit[3:2] interface mode bit 3 ? ident bit 2 ? mfm =11 at mode (default) =10 (reserved) =01 ps/2 =00 model 30 bit[4] swap drives 0,1 mode =0 no swap (default) =1 drive and motor sel 0 and 1 are swapped bit[5] fdc shutdown =0 FDC37N972 fdc operates normally, fdc pins are active (default) =1 fdc core is shutdown, only i/o writes to dor, tdr, dsr and ccr are enabled, all floppy disk interface pins tri-state except for drvden0, drvden1, nds0, nds1, nmtr0, and nmtr1. bit[6] fdc output type control =0 fdc outputs are od24 open drain (default) =1 fdc outputs are o24 push pull bit[7] fdc output control =0 fdc outputs active (default) =1 fdc outputs tri-stated bits 6 and 7 do not reflect the parallel port fdc pins. c fdd option register default = 0x00 0xf1 r/w bit[1:0] reserved, set to ?0? bit[3-2] density select =00 normal (default) =01 normal (reserved for users) =10 (forced to logic ?1?) =11 (forced to logic ?0?) bit[5:4] reserved bit[7:6] boot floppy =00 fdd 0 (default) =01 fdd 1 =10 fdd 2 =11 fdd 3 c
320 name reg index definition state fdd type register default = 0xff 0xf2 r/w bit[1:0] floppy drive a type bit[3:2] floppy drive b type bit[5:4] floppy drive c type bit[7:6] floppy drive d type c 0xf3 r reserved, read as 0 (read only) c fdd0 default = 0x00 0xf4 r/w bit[1:0] drive type select bit[2] read as ?0? (read only) bit[3:4] data rate table select bit[5] read as ?0? (read only) bit[6] precomp disable bit[7] read as ?0? (read only) c fdd1 0xf5 r/w refer to definition and default for 0xf4 c dt0 dt1 drvden0 (1) drvden1 (1) drive type 0 0 densel drate0 4/2/1 mb 3.5? 2/1 mb 5.25? fdds 2/1.6/1 mb 3.5? (3- mode) 0 1 drate1 drate0 1 0 ndensel drate0 1 1 drate0 drate1 there are four of the following registers in the configuration data space, one for each drive. fdd0 - 0xf4/fdd1 - 0xf5 d7 d6 d5 d4 d3 d2 d1 d0 0 pts 0 drt1 drt0 0 dt0 dt1 pts = 0 use precompensation, = 1 no precompensation dtx = drive type select drtx = data rate table select densel, drate1 and drate0 map onto three output pins drvden0 and drvden1.
321 table 220 - parallel port, logical device 3 [logical device number = 0x03] name reg index definition state pp mode register default = 0x3c 0xf0 r/w bit [2:0] parallel port mode = 100 printer mode (default) = 000 standard and bi-directional (spp) mode = 001 epp-1.9 and spp mode = 101 ep p-1.7 and spp mode = 010 ecp mode = 011 ecp and epp-1.9 mode = 111 ecp and epp-1.7 mode bit[6:3] ecp fifo threshold 0111b (default) bit[7] pp interrupt type not valid when the parallel port is in the printer mode (100) or the standard $ bi-directional mode (000) =1 pulsed low, released to high-z (665/666) =0 irw follows nack when parallel port in epp mode or [printer, spp, epp] under ecp, test or centronics fifo mode. c parallel port cnfgb shadow register default = 0x00 0xf1 r/w bit [2:0] parallel port dma channel select = 000 h/w jumpered 8-bit dma (default) = 001 dma channel 1 = 010 dma channel 2 = 011 dma channel 3 bit [5:3] parallel port irq line select = 000 h/w jumpered irq (default) = 001 irq 7 = 010 irq 9 = 011 irq 10 = 100 irq 11 = 101 irq 14 = 110 irq 15 = 111 irq 5 bit [7:6] reserved, ignores writes returns ?0? on reads. the dma/irq bits in this register are reflected in the enhanced parallel port?s read only cnfgb register. c
322 table 221 - serial port 1, logical device 4 [logical device number = 0x04] name reg index definition state serial port 1 mode register default = 0x00 0xf0 r/w bit[0] midi mode = 0 midi support disabled (default) = 1 midi support enabled bit[1] high speed = 0 high speed disabled (default) = 1 high speed enabled bit[6:2] reserved, set to ?0? bit[7] reserved c table 222 - infrared, logical device 5 [logical device number = 0x05] name reg index definition state infrared mode register default = 0x00 oxf0 r/w bit[0] midi mode =0 midi support disabled (default) =1 midi support enabled bit[1] high speed =0 high speed disabled (default) =1 high speed enabled bit[7:2] reserved c
323 name reg index definition state ir option register default = 0x00 this register sets the ir options and uses the same bit definitions as the fdc37c93x oxf1 r/w bit[0] receive polarity =0 active high =1 active low (default) bit[1] transmit polarity =0 active high (default) =1 active low bit[2] duplex select =0 full duplex (default) =1 half duplex bit[5:3] uart/ir mode =000 standard comm (default) =001 irda sir-a =010 ask-ir =011 (irda sir-b) =100 (irda hdlc) =101 (irda 4ppm) =110 (consumer) =111 (raw ir) bit[7:6] ircc 2.0 output mux =00 active device to com-rx/com- tx port (default) =01 active device to irrx/irtx port =10 reserved-use aux port not mapped to pins thus both ir and com ports are inactive =11 reserved, all ports are inactive c
324 name reg index definition state ir half duplex timeout default = 0x03 0xf2 r/w bit[7:0] these bits set the half duplex time-out for the ir port. this value is 0 to 10ms in 100 m s increments =0x00 blank rx/tx during transmit/receive =0x01 blank tx/tx during xmit/rcv + 100 m s ...... =0x64 blank rx/tx during xmit/rcv +10ms =0x65 - 0xff : reserved en_1 : bits [5:0] of the ir option configuration register must be reconciled with bits[5:0] of the ?sce configuration register a? control register in the ircc 2.0 block, detailed in the ircc 2.0 specification. additionally bits [7:6] of the ir option configuration register must be reconciled with bits[5:4] of the ?sce configuration register b? control register in the ircc 2.0 block. the last register written should update the information in both registers. both sets of registers can use common latches to store the information. table 223 - rtc, logical device 6 [logical device number = 0x06] name reg index definition state rtc mode register default = 0x00 0xf0 r/w bit[0] = 1 : lock cmos ram 80-9fh bit[1] = 1 : lock cmos ram a0-bfh bit[2] = 1 : lock cmos ram c0-dfh bit[3] = 1 : lock cmos ram e0-feh bit[7:4] reserved, set to ?0? once set, bit[3:0] can not be cleared by a write; bits[3:0] are cleared on vcc2 power on reset, vcc2 power off, or upon a hard reset (nreset_out asserted). once lock bits are set, both the host and the 8051 are locked out of accessing the locked locations as long as vcc1 and vcc2 are active. when vcc2 goes to 0v, the lock bits are cleared and the 8051 can access this ram while nreset_out is asserted. c
325 name reg index definition state rtc cmos bank 0 index register oxf1 r shadowed rtc/cmos bank 0 index register table 224 - kybd, logical device 7 [logical device number = 0x07] name reg index definition state krst_ga20 0xf0 r/w bit[0] : enab_p92 = 0 : port 92 disabled = 1 : port 92 enabled bit[7:0] : reserved, set to ?0?. note : refer to the 8051 section for descriptions of these registers. system shadow registers the FDC37N972 makes the following control registers readable by supplying a set of index registers accessable either through logical device 7 when in configuration state or through the open mode index and data registers when in run state. sys. index sys r/w 8051 address (7f00+) 8051 r/w power source vcc1 por vcc2 por zero wait state (9) notes force diskchange mbx99 r ------ n/a vcc2 03h ------ floppy data rate select shadow register mbx9a r ------ n/a vcc2 n/a ------ uart1 fifo control shadow register mbx9b r ------ n/a vcc2 00h
326 floppy data rate select shadow register d7 d6 d5 d4 d3 d2 d1 d0 8051 r/w n/a n/a n/a n/a n/a n/a n/a n/a system r/w r r r r r r r r bit def soft reset power down 0 pre- comp 2 pre- comp 1 pre- comp 0 data rate select 1 data rate select 0 note: d1 and d0 are updated by a write to the floppy data rate or ccr registers. bits d7-d2 are updated by a write to the floppy data rate register only. force diskchange d7-d2 d1 d0 system r/w r r/w r/w bit def reserved 1 = force a diskchange indication when the dir register (of the floppy controller) is read, gated with drive select 0 or 1. these bits can be written to a ?1? but are not clearable by the software. these bits are reset when nstep input is active with the proper drive select to the drive occurs. d0 is cleared on nstep and drive select 0; d1 is cleared on nstep and drive select 1. equivalent logic: when read dir bit 7 = (drive_sel_0 & d0) or (drive_sel_1 & d1) or dsk_chg
327 electrical specifications maximum guaranteed ratings* operating temperature range ................................ ................................ ......................... 0 o c to +70 o c storage temperature range ................................ ................................ .......................... -55 o to +150 o c lead temperature range (soldering, 10 seconds) ................................ ................................ .... +325 o c positive voltage on any pin, with respect to ground ................................ ................................ .... +5.5v negative voltage on any pin, with respect to ground ................................ ................................ .... -0.3v supply voltage range v cc 1 and v cc 2 ................................ ................................ ............ v cc 1 and v cc 2 *stresses above those listed above could cause permanent damage to the device. this is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. note : when powering this device from laboratory or system power supplies, it is important that the absolute maximum ratings not be exceeded or device failure can result. some power supplies exhibit voltage spikes on their outputs when the ac power is switched on or off. in addition, voltage transients on the ac power line may appear on the dc output. if this possibility exists, it is suggested that a clamp circuit be used. table 223 - operating conditions symbol parameter min typ max units vcc0 vbat for rtc 2.4 3.0 3.3 v vcc1 vcc for 8051 3.15 3.3 3.45 v vcc2 system vcc 3.15 3.3 3.45 v pci_clk pci clock 33 mhz xtal1/xtal2 rtc crystal 32.768 khz clocki 14.318 clock input 14.318 mhz power comsumption in various states v cc2 (vdc) v cc1 (vdc) 8051 state clock state sym typ max comments 3.3 3.3 run 24 mhz i cc2 i cc1 15 ma 24 ma 20 ma 30 ma floppy @ 1 meg data rate i2c @ 24 mhz 3.3 3.3 run 12 mhz i cc2 i cc1 13 ma 12 ma 15 ma 18 ma floppy @ 500k data rate i2c @ 12 mhz 3.3 3.3 run ring osc i cc2 i cc1 >1ma 8 ma 2 ma 10 ma pll on i2c off 3.3 3.3 idle ring osc i cc2 i cc1 >1ma 5 ma 2 ma 7 ma pll off 0 3.3 run ring osc i cc2 i cc1 8 ma 10 ma pll off i2c off 0 3.3 idle ring osc i cc2 i cc1 6 ma 8 ma pll off i2c off
328 v cc2 (vdc) v cc1 (vdc) 8051 state clock state sym typ max comments 0 3.3 sleep stop i cc1 160 a xosel=1 0 3.3 sleep stop i cc1 5 a 10 a xosel=0 0 0 i cc0 40 a 60 a 2.4 < v cc0 < 4 vdc, xosel=1, 0 0 i cc0 0.4 a 1.5 a 2.4 < v cc0 < 4 vdc, xosel = 0 note: when a single-ended 32.768khz clock source is selected (see se ction 32khz clock input. the FDC37N972 uses the xosel pin to select either a 32.768khz input clock or a 32.768khz crystal to drive the real time clock interface (table 2 - pin function description). when xosel = ?0?, the rtc uses a 32.768khz crystal connected between the xtal1 and xtal2 pins. when xosel = ?1?, the rtc is driven by a 32.768khz single- ended clock source connected to the xtal2 pin. dc specifications dc electrical characteristics (t a = 0c - 70c, v cc 1 and v cc 2= v cc 1 and v cc 2) parameter symbol min typ max units comments i type input buffer low input level high input level v ili v ihi 2.0 0.8 v v ttl levels is type input buffer low input level high input level schmitt trigger hysteresis v ilis v ihis v hys 2.2 250 0.8 v v mv schmitt trigger schmitt trigger isp type input buffer with 90 m m a weak pull-up low input level high input level schmitt trigger hysteresis v ilis v ihis v hys 2.2 250 0.8 v v mv schmitt trigger schmitt trigger i clk input buffer low input level high input level v ilck v ihck 3.0 0.4 v v o clk2 crystal oscillator output i clk2 crystal oscillator input use a 32 khz parallel resonant crystal oscillator. the load capacitors are seen by the crystal as two capacitors in series and should be approximately 2 times the co of the actual crystal used (c1=2co). for example, a 7.5pf crystal should use two 15pf capacitors for proper loading.
329 parameter symbol min typ max units comments input leakage (all i and is buffers except pwrgd & vcc1_pwrgd) low input leakage high input leakage i il i ih -10 -10 +10 +10 m a m a v in = 0 v in = v cc input current pwrgd i oh 75 150 m a v in = 0 o4 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.4 +10 v v m a i ol = 4 ma i oh = -2 ma v in = 0 to v cc od4 type buffer low output level output leakage v ol i oh -10 0.4 +10 v m a v ol = 4 ma i oh = 0 to v cc o8 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.4 +10 v v m a i ol = 8 ma i oh = -4 ma v in = 0 to v cc od8 type buffer low output level output leakage v ol i oh -10 0.4 +10 v m a v ol = 8 ma i oh = 0 to v c c o24 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.4 +10 v v m a i ol = 24 ma i oh = -12 ma v in = 0 to v cc od24 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.4 +10 v v m a i ol = 24 ma i oh = -50 ma v in = 0 to v cc
330 parameter symbol min typ max units comments io12 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.4 +10 v v a i ol = 12ma i oh = -6ma v in = 0 to v cc (note 2) io8 type buffer low output level high output level output leakage input leakage (all i and is buffers except fad[7:0] v ol v oh i ol 2.4 -10 0.4 +10 v v a i ol = 8ma i oh = -4ma v in = 0 to v cc (note 2) fad[7:0] input leakage low input leakage high input leakage i il i ih -100 -100 +100 +100 na na v i n = 0 v in = v cc iod8 type buffer low output level high input level high inputt level output leakage v ol v ih v il 0.5 2.0 0.8 v v v i ol =8 ma iod16 type buffer low output level high input level high inputt level output leakage v ol v ih v il 0.5 2.0 0.8 v v v i ol =16 ma
331 parameter symbol min typ max units comments iop14 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.4 +10 v v a i ol = 14ma i oh = -14ma v in = 0 to v cc (note 2) ip type buffer low input level high input level v ili v ihi 2.0 0.8 v v o12 type buffer low output level high output level v ol v oh 2.4 0.4 v v i ol = 12ma i oh = -6ma od12 type buffer low output level output leakage v ol i ol -10 0.4 +10 v a i ol = 12ma v in = 0 to v cc od14 type buffer low output level output leakage v ol i ol -10 0.4 +10 v a i ol = 14ma v in = 0 to v cc od16 type buffer low output level output leakage v ol i ol -10 0.4 +10 v a i ol = 16ma v in = 0 to v cc op14 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.4 +10 v v a i ol = 14ma i oh = -14ma v in = 0 to v cc (note 2)
332 parameter symbol min typ max units comments pci_clk type buffer see specification for pci systems version 6.0 pci_io type buffer see specification for pci systems version 6.0 pci_od type buffer see specification for pci systems version 6.0 iclk type buffer low input level high input level v ili v ihclk 2.4 0.4 v v iclk2 type buffer oclk2 type buffer use a 32 khz parellel rosinant cystal oscillator. the load copacitors are seen by the crystal as tow capacitors in series and should be approximately 2 times the c 0 of the actual crystal used (c1- c o .) for example a 7.5 pf cyrstal should use two 15 pf capacitors for proper loading. supply current active supply current sleep i cc i slp 50 25 ma m a i cc2 + i cc1 (note 1) i cc1 with v cc2 off, sleep mode notes: 1) this value is with the fdc at less than 2 mhz, and the 8051running at the ring oscillator drawing 8ma. the max value is 60ma with the fdc at 2 mhz. the ring oscillator is typically 4 ? 8 mhz. 2) all output leakage?s are measured with the current pins in high impedance ac specifications ac test conditions capacitance t a = 25c; fc = 1mhz; v cc = 5v limits parameter symbol min typ max unit test condition clock input capacitance c in 20 pf input capacitance c in 10 pf output capacitance c out 20 pf all pins except pin under test tied to ac ground
333 timing diagrams load capacitance for the timing diagrams shown, the following capacitive loads are used. table 226 - capacitive loading name capacitance total (pf) name capacitance total (pf) sd[0:7] 240 emclk 240 iochrdy 240 emdat 240 nirq8 120 imclk 240 nsmi 120 imdat 240 drq[0:1] 120 kbdat 240 32khz_out 50 kbclk 240 24mhz_out 50 ps2dat 240 nwgate 240 ps2clk 240 nwdata 240 nnows 240 nhdsel 240 fad[0:7] 100 ndir 240 fa[8:17] 100 nstep 240 nfrd 50 nds[1:0] 240 nfwr 50 nmtr[1:0] 240 fale 50 drvden[1:0] 240 kso[0:13] 100 txd1 100 sirq 150 nrts1 100 fpd 50 ndtr1 100 ab_data 100 pd[0:7] 240 ab_clk 100 nslctin 240 irtx 50 ninit 240 pwm[0:1] 50 nalf 240 nreset_out 240 nstrobe 240
334 fast gatea20 iow timing t3 t4 t1 t2 t5 sa[x] sd[7:0] niow figure 51 - fast gatea20 iow timing in order to use the fastgatea20 speed-up mechanism, data must be available by the falling edge of niow. table 227 - fast gatea20 iow timing parameters name description min typ max units t1 sa[x] valid to niow asserted 10 ns t2 sd[7:0] valid to niow asserted 0 ns t3 niow asserted to sa[x] invalid 10 ns t4 niow deasserted to sd[7:0] invalid 0 ns t5 niow deasserted to niow or nior asserted 100 ns
335 isa io write t10 t3 t1 t2 t4 t6 t5 t7 t8 t9 data valid aen sa[x] niow sd[x] fintr pintr ibf figure 52 - isa io write table 228 - isa io write parameters name descrip tion min typ max units t1 sa[x] and aen valid to niow assert ed 10 ns t2 niow assert ed to niow deasserted 80 ns t3 niow assert ed to sa[x] in valid 10 ns t4 sd[x] valid to niow deasserted 45 ns t5 sd[x] hold from niow deasserted 0 ns t6 niow deasserted to niow assert ed 25 ns t7 niow deasserted to fintr deasserted (note 1) 55 ns t8 niow deasserted to pinter deasserted (note 2) 260 ns t9 ibf (internal sig nal) assert ed from niow deasserted 40 ns t10 niow deasserted to aen invalid 10 ns note 1: fintr refers to the irq used by the flopp y disk logical device. note 2: pintr refers to the irq used by the parallel port logical device.
336 isa io read cycle t13 t3 t1 t7 t2 t6 t4 t5 t10 t9 t11 t12 t8 data valid aen sa[x] nior sd[x] pd[x], nerror, pe, slct, ack, busy finter pinter pcobf auxobf1 nior/niow figure 53 - isa io read cycle table 229 - isa io read timing parameters name description min typ max units t1 sa[x] and aen valid to nior asserted 10 ns t2 nior asserted to nior deasserted 50 ns t3 nior asserted to sa[x] invalid 10 ns t4 nior asserted to data valid 50 ns t5 data hold/float from nior deasserted 10 25 ns t6 nior deasserted to nior asserted 25 ns t8 nior asserted after niow deasserted 80 ns t8 nior/nior, niow/niow transfers from/to ecp fifo 150 ns t7 parallel port setup to nior asserted 20 ns t9 nior asserted to pinter deasserted 55 ns t10 nior deasserted to finter deasserted 260 ns t11 nior deasserted to pcobf deasserted (notes 3,5) 80 ns
337 name description min typ max units t12 nior deasserted to auxobf1 deasserted (notes 4,5) 80 ns t13 nior deasserted to aen invalid 10 ns note 1: fintr refers t o the irq used by the floppy disk. note 2: pintr refers to the irq used by the parallel port. note 3: pcobf is used for the keyboard irq. note 4: auxobf1 is used for the mouse irq. note 5: applies only if deassertion is performed in hardware.
338 figure 54 - input clock timing table 230 - input clock timing parameters name description min typ max units t1 clock cycle time for 14.318 mhz (note) 69.84 ns t2 clock high time/low time for 14.318 mhz 15 ns t r , t f clock rise time/fall time (not shown) 5 ns note: tolerance is 0.01 % . t2 t1 t2 clocki
339 dma timing (single transfer mode) t15 t2 t3 t12 t16 t1 t4 t5 t6 t11 t14 t8 t7 t9 t10 t13 aen fdrq, pdrq ndack nior or niow data (do-d7) tc data valid figure 55 - dma timing (single transfer mode) table 231 - dma timing (single transfer mode) parameters name description min typ max units t1 ndack delay time from fdrq high 0 ns t2 drq reset delay from nior or niow 100 ns t3 fdrq reset delay from ndack low 100 ns t4 ndack width 150 ns t5 nior delay from fdrq high 0 ns t6 niow delay from fdrq high 0 ns t7 data access time from nior low 100 ns t8 data set up time to niow high 40 ns t9 data to float delay from nior high 10 60 ns t10 data hold time from niow high 10 ns t11 ndack set up to niow/nior low 5 ns t12 ndack hold after niow/nior high 10 ns t13 tc pulse width 60 ns t14 aen set up to nior/niow 40 ns t15 aen hold from ndack 10 ns t16 tc active to pdrq inactive 100 ns
340 dma timing (burst transfer mode) t15 t2 t3 t12 t16 t1 t4 t5 t6 t11 t14 t8 t7 t9 t10 t13 aen fdrq, pdrq ndack nior or niow data (do-d7) tc data valid data valid figure 56 - dma timing (burst transfer mode) table 232 - dma timing (burst transfer mode) parameters name description min typ max units t1 ndack delay time from fdrq high 0 ns t2 drq reset delay from nior or niow 100 ns t3 fdrq reset delay from ndack low 100 ns t4 ndack width 150 ns t5 nior delay from fdrq high 0 ns t6 niow delay from fdrq high 0 ns t7 data access time from nior low 100 ns t8 data set up time to niow high 40 ns t9 data to float delay from nior high 10 60 ns t10 data hold time from niow high 10 ns t11 ndack set up to niow/nior low 5 ns t12 ndack hold after niow/nior high 10 ns t13 tc pulse width 60 ns t14 aen s et u p to n ior/ n iow 40 ns t15 aen hold from ndack 10 ns t16 tc active to pdrq inactive 100 ns
341 floppy disk drive timing (at mode) t3 t1 t2 t4 t5 t6 t7 t8 t9 t9 ndir nstep nds0-3 nindex nrdata nwdata niow nds0-3, mtr0-3 figure 57 - floppy disk drive timing (at mode) table 233 - floppy disk drive timing (at mode) parameters name description min typ max units t1 ndir set up to step low 4 x* t2 nstep active time low 24 x* t3 ndir hold time after nstep 96 x* t4 nstep cycle time 132 x* t5 nds0-3 hold time from nstep high 20 x* t6 nindex pulse width 2 x* t7 nrdata active time low 40 ns t8 nwdata write data width low .5 y* t9 nds0-3, mtro-3 from end of niow 25 ns *x specifies one mclk period and y specifies one wclk period. mclk = controller clock to fdc wclk = 2 x data rate
342 serial port timing t1 t5 t2 t4 t6 t3 niow nrtsx, ndtrx irqx nctsx, ndsrx, ndcdx irqx niow irqx nior nri figure 58 - serial port timing table 234 - serial port timing parameters name description min typ max units t1 nrtsx, ndtrx delay from niow 200 ns t2 irqx active delay from nctsx, ndsrx, ndcdx 100 ns t3 irqx inactive delay from nior (leading edge) 120 ns t4 irqx inactive delay from niow (trailing edge) 125 ns t5 irqx inactive delay from niow 10 100 ns t6 irqx active delay from 0x 100 ns
343 parallel port timing t1 t4 t3 t2 t2 t5 t3 niow ninit, nstrobe. nautofd, slctin nack pintr (ecp or epp enabled) nfault (ecp) nerror (ecp) pintr pd0- pd7 t6 npintr (spp) figure 59 - parallel port timing table 235 - parallel port timing parameters name description min typ max units t1 pd0-7, ninit, nstrobe, nalf delay from niow 100 ns t2 pintr delay from nack, nfault 60 ns t3 pintr active low in ecp and epp modes 200 300 ns t4 pintr delay from nack 105 ns t5 nerror active to pintr active 105 ns t6 pd0 - pd7 delay from iow active 100 ns
344 epp 1.9 data or address write cycle t18 t9 t8 t17 t12 t19 t10 t11 t13 t20 t2 t1 t5 t3 t14 t16 t4 t6 t15 t7 a0-a10 sd<7:0> niow iochrdy nwrite pd<7:0> ndatast naddrstb nwait figure 60 - epp 1.9 data or address write cycle table 236 - epp 1.9 data or address write parameters name description min typ max units t1 niow asserted to pdata valid 0 50 ns t2 nwait asserted to nwrite change (note 1) 60 185 ns t3 nwrite to command asserted 5 35 ns t4 nwait deasserted to command deasserted (note 1) 60 190 ns t5 nwait asserted to pdata invalid (note 1) 0 ns t6 time out 10 12 m s t7 command deasserted to nwait asserted 0 ns t8 sdata valid to niow asserted 10 ns t9 niow deasserted to data invalid 0 ns t10 niow asserted to iochrdy deasserted 0 24 ns t11 nwait deasserted to iochrdy asserted (note 1) 60 160 ns t12 iochrdy asserted to niow deasserted 10 ns t13 niow asserted to nwrite asserted 0 70 ns t14 nwait asserted to command asserted (note 1) 60 210 ns t15 command asserted to nwait deasserted 0 10 m s t16 pdata valid to command asserted 10 ns
345 name description min typ max units t17 ax valid to niow asserted 40 ns t18 niow deasserted to ax invalid 10 ns t19 niow deasserted to niow or nior asserted 40 ns t20 nwait asserted to nwrite asserted (note 1) 60 185 ns note 1: nwait must be filtered to compensate for ringing on the parallel bus cable. wait is considered to have settled after it does not transition for a minimum of 50 nsec.
346 epp 1.9 data or address read cycle t20 t19 t11 t22 t13 t12 t8 t10 t18 t9 t21 t17 t2 t5 t4 t16 t1 t14 t28 t3 t7 t15 t6 pdata bus driven by peripheral a0-a10 ior sd<7:0> iochrdy nwrite pd<7:0> datastb addrstb nwait figure 61 - epp 1.9 data or address read cycle table 237 - epp 1.9 data or address read cycle timing parameters name description min typ max units t1 pdata h i -z to c ommand a sserted 0 30 ns t2 nior asserted to pdata hi-z 0 50 ns t3 nwait deasserted to command deasserted (note 1) 60 180 ns t4 command deasserted to pdata hi-z 0 ns t5 command asserted to pdata valid 0 ns t6 pdata hi-z to nwait deasserted 0 m s t7 pdata valid to nwait deasserted 0 ns t8 nior asserted to iochrdy deasserted 0 24 ns t9 nwrite deasserted to nior asserted (note 2) 0 ns t10 nwait deasserted to iochrdy asserted (note 1) 60 160 ns t11 iochrdy asserted to nior deasserted 0 ns t12 nior deasserted to sdata hi-z (hold time) 0 40 ns t13 pdata valid to sdata valid 0 75 ns t14 nwait asserted to command asserted 0 195 ns
347 name description min typ max units t15 time out 10 12 m s t16 nwait deasserted to pdata driven (note 1) 60 190 ns t17 nwait deasserted to nwrite modified (notes 1,2) 60 190 ns t18 sdata valid to iochrdy deasserted (note 3) 0 85 ns t19 ax valid to nior asserted 40 ns t20 nior deasserted to ax invalid 10 10 ns t21 nwait asserted to nwrite deasserted 0 185 ns t22 nior deasserted to niow or nior asserted 40 ns t28 nwrite deasserted to command 1 ns note 1: nwait is considered to have settled after it does not transition for a minimum of 50 ns. note 2: when not executing a write cycl e, epp nwrite is inactive high. note 3: 85 is true only if t7 = 0.
348 epp 1.7 data or address write cycle t18 t9 t8 t17 t6 t12 t19 t10 t20 t11 t13 t2 t1 t5 t3 t16 t4 t21 a0-a10 sd<7:0> niow iochrdy nwrite pd<7:0> ndatast naddrstb nwait figure 62 - epp 1.7 data or address write cycle table 238 - epp 1.7 data or address write cycle timing parameters name description min typ max units t1 niow asserted to pdata valid 0 50 ns t2 command deasserted to nwrite change 0 40 ns t3 nwrite to command 5 35 ns t4 niow deasserted to command deasserted (note 2) 50 ns t5 command deasserted to pdata invalid 50 ns t6 time out 10 12 m s t8 sdata valid to niow asserted 10 ns t9 niow deasserted to data invalid 0 ns t10 niow asserted to iochrdy deasserted 0 24 ns t11 nwait deasserted to iochrdy asserted 40 ns t12 iochrdy asserted to niow deasserted 10 ns
349 name description min typ max units t13 niow asserted to nwrite asserted 0 50 ns t16 pdata valid to command asserted 10 35 ns t17 ax valid to niow asserted 40 ns t18 niow deasserted to ax invalid 10 m s t19 niow deasserted to niow or nior asserted 100 ns t20 nwait asserted to iochrdy asserted 45 ns t21 command deasserted to nwait deasserted 0 ns note 1: nwrite is controlled by clearing the pdir bit to "0" in the control register before performing an epp write. note 2: the n umber is only valid if nwait is active when iow goes active.
350 epp 1.7 data or address read cycle t20 t19 t11 t15 t22 t13 t12 t3 t8 t10 t5 t4 t23 t2 t21 a0-a10 nior sd<7:0> iochrdy nwrite pd<7:0> ndatastb naddrstb nwait figure 63 - epp 1.7 data or address read cycle table 239 - epp 1.7 data or address read cycle timing parameters name description min typ max units t2 nior deasserted to command deasserted 50 ns t3 nwait asserted to iochrdy deasserted 0 40 ns t4 command deasserted to pdata hi-z 0 ns t5 command asserted to pdata valid 0 ns t8 nior asserted to iochrdy asserted 24 ns t10 nwait deasserted to iochrdy deasserted 50 ns t11 iochrdy deasserted to nior asserted 0 ns t12 nior deasserted to sdata high-z (hold time) 0 40 ns t13 pdata valid to sdata valid 40 ns t15 time out 10 12 m s t19 ax valid to nior asserted 40 ns t20 nior deasserted to ax invalid 10 ns t21 command deasserted to nwait deasserted 0 ns t22 nior deasserted to niow or nior asserted 40 ns t23 nior asserted to command asserted 55 ns note: writ e is controlled by setting the pdir bit to "1" in the control register before performing an epp read.
351 ecp parallel port timing parallel port fifo (mode 101) the standard parallel port is run at or near the peak 500kbytes/sec allowed in the forward direction using dma. the state machine does not examine nack, but begins the next transfer based on busy. refer to figure 55 . ecp parallel port timing the timing is designed to allow operation at approximately 2.0 mbytes/sec over a 15ft. cable. if a shorter cable is used then the bandwidth will increase. forward-idle when the host has no data to send it keeps hostclk () high and the peripheral will leave periphclk (busy) low. forward data transfer phase the interface transfers data and commands from the host to the peripheral using an inter- locked periphack and hostclk. the peripheral may indicate its desire to send data to the host by asserting nperiphrequest. the forward data transfer phase may be entered from the forward-idle phase. while in the forward phase the peripheral may asynchronously assert the nperiphrequest (nfault) to request that the channel be reversed. when the peripheral is not busy it sets periphack (busy) low. the host then sets hostclk (nstrobe) low when it is pre pared to send data. the data must be stable for the specified setup time prior to the falling edge of hostclk. the peripheral then sets periphack (busy) high to acknowledge the handshake. the host then sets hostclk (nstrobe) high. the peripheral then accepts the data and sets periphack (busy) low, completing the transfer. this sequence is shown in figure 59 . the timing is designed to provide 3 cable round -trip times for data setup if data is driven simultaneously with hostclk (nstrobe). reverse -idle phase the peripheral has no data to send and keeps periphclk high. the host is idle and keeps hostack low. reverse data transfer phase the interface transfers data and commands from the peripheral to the host using an interlocked hostack and periphclk. the reverse data transfer phase may be en- tered from the reverse-idle phase. after the previous byte has beed accepted the host sets hostack (nalf) low. the peripheral then sets periphclk (nack) low when it has data to send. the data must be stable for the specified setup time prior to the falling edge of periphclk. when the host is ready it to accept a byte it sets hostack (nalf) high to acknowledge the handshake. the peripheral then sets periphclk (nack) high. after the host has accepted the data it sets hostack (nalf) low, completing the transfer. this sequence is shown in figure 57 - floppy disk drive timing (at mode) output drivers to facilitate higher performance data transfer, the use of balanced cmos active drivers for critical signals (data, hostack, hostclk, periphack, periphclk) are used ecp mode. because the use of active drivers can present compatibility problems in compatible mode (the control signals, by tradition, are speci- fied as open -collector), the drivers are dynam- ically changed from open -colle ctor to totem -pole. the timing for the dynamic driver change is specified in the ieee 1284 extended capabilities port protocol and isa
352 interface standard , rev. 1.14, july 14, 1996, available from microsoft. the dynamic driver change must be implement ed properly to prevent glitching the outputs. t3 t6 t1 t2 t5 t4 pdata nstrobe busy figure 64 - parallel port fifo timing table 240 - parallel port fifo timing parameters name description min typ max units t1 data valid to nstrobe active 600 ns t2 nstrobe active pulse width 600 ns t3 data hold from nstrobe inactive (note 1) 450 ns t4 nstrobe active to busy active 500 ns t5 busy inactive to nstrobe active 680 ns t6 busy inactive to pdata invalid (note 1) 80 ns note 1: the data is held until busy goes inactive or for time t3, whichever is longer. this only applies if another data transfer is pending. if no other data transfer is pending, the data is held indefinitely.
353 t3 t4 t1 t2 t7 t8 t6 t5 t6 nautofd pdata<7:0> busy nstrobe figure 65 - ecp parallel port forward timing table 241 - ecp parallel port forward timing parameters name description min typ max units t1 nalf valid to nstrobe asserted 0 60 ns t2 pdata valid to nstrobe asserted 0 60 ns t3 busy deasserted to nalf changed (notes 1,2) 80 180 ns t4 busy deasserted to pdata changed (notes 1,2) 80 180 ns t5 nstrobe deasserted to busy asserted 0 ns t6 nstrobe deasserted to busy deasserted 0 ns t7 busy deasserted to nstrobe asserted (notes 1,2) 80 200 ns t8 busy asserted to nstrobe deasserted (note 2) 80 180 ns note 1: maximum value only applies if there is data in the fifo waiting to be written out. note 2: busy is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns.
354 t2 t1 t5 t6 t4 t3 t4 pdata<7:0> nack nautofd figure 66 - ecp parallel port reverse timing table 242 - ecp parallel port reverse timing name description min typ max units t1 pdata valid to nack asserted 0 ns t2 nalf deasserted to pdata changed 0 ns t3 nack asserted to nalf deasserted (notes 1,2) 80 200 ns t4 nack deasserted to nalf asserted (note 2) 80 200 ns t5 nalf asserted to nack asserted 0 ns t6 nalf deasserted to nack deasserted 0 ns note 1: maximum valu e only applies if there is room in the fifo and terminal count has not been received. ecp can stall by keeping nalf low. note 2: nack is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns.
355 access.bus timing t hd;sta t su;sto t su;sta t su;dat t high t f t r t low t hd;dat t hd;sta t buf ab_data ab_clk figure 67 - access.bus timing table 243 - access.bus timing parameters symbol parameter min. typ. max. unit f scl scl clock frequency 100 khz t buf bus free time 4.7 s t su ; sta start condition set-up time 4.7 s t hd ; sta start condition hold time 4.0 s t low scl low time 4.7 s t high scl high time 4.0 s t r scl and sda rise time 1.0 s t f scl and sda fall time 0.3 s t su ; dat data set-up time 0.25 s t hd ; dat data hold time 0 s t su ; sto stop condition set-up time 4.0 s
356 host flash read timing tsu1 tsu2 t10 t11 t17 t5 t1 t18 t2 t4 t21 t19 t2 t4 t8 t14 t15 t21 t19 t7 t13 t3 t6 t16 t20 t9 t12 a[7:0] a[15:0] hmem[1:0]=a[17:16] kmem[2:1] a[15:8] d[7:0] d[7:0] 8051port0 a[7:0] kmem[2:1] 8051adr[14:8],kmem[0] 8051adr[14:8],kmem[0] 8051port0 8051stopped sa[15:0] sd[7:0] nrom_cs nmemrd nmemwr fa[17:16] fa[15:8] fad[7:0] iochrdy fale nfrd nfwr figure 68 - host flash read timing
357 table 244 - host flash read timing parameters parameter min typ max units t1 8051 stopped condition met to fa[17:16] sourced by internal register hmem[1:0] 40 ns t2 8051 stopped condition met to fa[15:0] driven by sa[15:0] 40 ns t3 8051 stopped condition met to fale asserted 40 ns t4 sa[15:0] valid to fa[15:0] valid propogation delay 40 ns t5 sa[15:0] valid to nmemrd asserted 88 ns t6 nmemrd asserted to fale de-asserted 21 63 ns t7 nmemrd asserted to iochrdy de-asserted (note1) 24 ns t8 fale de-asserted to fad[7:0] tristated 42 ns t9 fale de-asserted to nfrd asserted 84 ns t10 nmemrd asserted to sd[7:0] driven 30 ns t11 fad[7:0] data valid to sd[7:0] data valid propogation delay 40 ns t12 nfrd, flash read, asserted pulse width (note2) 120 [3 sclk] 200 [5 sclk] ns t13 nfrd de-asserted to iochrdy asserted 0 20 ns t14 fad[7:0] data hold time from nfrd de-asserted 0 ns t15 sa[7:0] muxed onto fad[7:0] following the de- assertion of nfrd 42 ns t16 nfrd de-asserted to fale asserted for next cycle 42 ns t17 sd[7:0] data hold time from nmemrd de-asserted 10 ns t18 8051 clock started condition met to fa[17:16] sourced by internal register kmem[2:1] 40 ns t19 8051 clock started condition met to fa[15] sourced by kmem[0] and fa[14:0] driven by the 8051 40 ns t20 8051 clock started condition met to fale de-asserted 40 ns t21 sa[15:0] invalid to fa[15:0] invalid propagation delay 40 ns tsu1 nrom_cs asserted to nmemrd setup time 20 ns tsu2 fad[7:0] data valid to nfrd de-asserted setup time 20 ns note 1: systems designed prior to the eis a specification, r3.12, which sample chrdy on the rising edge of bclk require that iochrdy is deasserted within 24 ns. note 2: the flash read signal pulse width is programmable through a configuration register, the time values shown are for an internal sclk=24 mhz derived from the 14.318 mhz input.
358 host flash read/write t16 tsu1 t17 t5 t1 t18 t2 t4 t21 t19 t2 t4 t9 t13 t14 t21 t19 t7 t12 t3 t6 t15 t20 t10 t11 a[7:0] a[15:0] hmem[1:0]=a[17:16] kmem[2:1] a[15:8] d[7:0] d[7:0] 8051port0 a[7:0] kmem[2:1] 8051adr[14:8],kmem[0] 8051adr[14:8],kmem[0] 8051port0 8051stopped sa[15:0] sd[7:0] nrom_cs nmemrd nmemwr fa[17:16] fa[15:8] fad[7:0] iochrdy fale nfrd nfwr figure 69 - host flash write timing parameters
359 table 245 - host flash write timing parameters parameter min typ max units t1 8051 stopped condition met to fa[17:16] sourced by internal register hmem[2:1] 40 ns t2 8051 stopped condition met to fa[15] driven by sa[15:0] 40 ns t3 8051 stopped condition met to fale asserted 40 ns t4 sa[15:0] valid to fa[15:0] valid propogation delay 40 ns t5 sa[15:0] valid to nmemwr asserted 88 ns t6 nmemwr asserted to fale de-asserted 21 63 ns t7 nmemwr asserted to iochrdy de-asserted (note 1) 24 ns t9 fale de-asserted to sd[7:0] driven onto fad[7:0] 42 ns t10 fale de-asserted to nfwr asserted 84 ns t11 nfwr, flash write, asserted pulse width (note 2) 120 [3 sclk] 200 [5 sclk] ns t12 nfwr de-asserted to iochrdy asserted 20 ns t13 fad[7:0] data hold time from nfwr de-asserted 42 ns t14 sa[7:0] muxed onto fad[7:0] following the de-assertion of nfwr 42 ns t15 nfwr deasserted to fale asserted for next cycle 42 ns t16 nmemwr asserted to sd[7:0] valid -10 ns t17 sd[7:0] data hold time from nmemwr de-asserted 10 ns t18 8051 clock started condition met to fa[17:16] sourced by internal register kmem[2:1] 40 ns t19 8051 clock started condition met to fa[15] sourced by kmem[0] and fa[14:0] driven by the 8051 40 ns t20 8051 clock started condition met to fale de-asserted 40 ns t21 sa[15:0] invalid to fa[15:0] invalid propagation delay 40 ns tsu1 nrom_cs asserted to nmemwr setup time 20 ns note 1: systems designed prior to the eisa specification, r3.12, which sample chrdy on the rising edge of bclk require that iochrdy is deasserted within 24 ns. note 2: the flash write signal pulse width is programmable through a configuration register, the time values shown are for an internal sclk=24 mhz derived from the 14.318 mhz input
360 zero wait state (nows) timing t1 t12 t11 t2 t3 t9 t4 t5 t6 t7 t8 t10 sa[15:0] aen nior, niow nnows read data write data figure 70 - zero wait state (nows) timing table 246 - zero wait-state timing parameters parameter min typ max units t1 aen valid before nior, niow asserted 10 ns t2 sa[15:0] valid before nior asserted 10 ns t3 nior, niow pulse width 80 ns t4 nior, niow asserted to nnows asserted 50 ns t5 nior, niow negated to nnows floated 35 ns t6 nior asserted to read data valid 50 ns t7 nior negated to read data invalid (hold time) 0 ns t8 nior negated to data bus floated 24 ns t9 write data valid before niow deasserted 45 ns t10 niow negated to write data invalid (hold time) 0 ns t11 nior, niow negated to aen invalid 10 ns t12 nior, niow negated to sa[15:0] invalid 10 ns
361 flash program fetch timing figure 71 - 8051 flash program fetch timing table 247 - 8051 flash program fetch timing parameters 8051 clock = 12 mhz parameter min typ max units t1 address valid to fale low 38 41 ns t2 address hold following fale low 35 60 ns t3 fale low to nfrd low 35 45 50 ns t4 nfrd pulse width 150 162 ns t5 nfrd high to fale high 0 5 10 ns t6 nfrd low to valid instruction 135 ns t7 instruction hold following nfrd 0 ns t8 instruction float following nfrd 80 ns 8051 clock = 24 mhz parameter @24 mhz min typ max units t1 address valid to fale low 15 20 ns t2 address hold following fale low 35 40 ns t3 fale low to nfrd low 18 23 30 ns t4 nfrd pulse width 60 82 ns t5 nfrd high to fale high 0 6 10 ns t6 nfrd low to valid instruction in 40 ns t7 instruction hold following nfrd 0 ns t8 instruction float following nfrd 40 ns min and max delays shown for an 8051 clock of 12 mhz and 24 mhz as indicated. device mode register bits [1:0] = 00 (see global configuration registers, table 214, address 0x25). t1 t5 t3 t4 t2 t6 t7 t8 insruction fa[17:8] fa[7:0] fa[17:8] fa[7:0 fale nfrd fad[7:0] fa[17:8]
362 8051 flash read timing t1 t5 t3 t4 t2 t6 t7 t8 data in fa[17:8] fa[7:0] fa[17:8] fa[7:0 fale nfrd fad[7:0] fa[17:8] figure 72 - 8051 flash read timiing table 248 - flash read timiing parameters 8051 clock = 12 mhz parameter min typ max units t1 address valid to fale low 38 41 ns t2 address hold following fale low 35 60 ns t3 fale low to nfrd low 35 45 50 ns t4 nfrd pulse width 150 162 ns t5 nfrd high to fale high 0 5 10 ns t6 nfrd low to valid data in 135 ns t7 data hold following nfrd 0 ns t8 data float following nfrd 80 ns 8051 clock =24 mhz parameter @24 mhz min typ max units t1 address valid to fale low 15 20 ns t2 address hold following fale low 35 40 ns t3 fale low to nfrd low 18 23 30 ns t4 nfrd pulse width 60 82 ns t5 nfrd high to fale high 0 6 10 ns t6 nfrd low to valid data in 40 ns t7 data hold following nfrd 0 ns t8 data float following nfrd 40 ns min and max delays shown for an 8051 clock of 12 mhz and 24 mhz as indicated. device mode register bits [1:0] = 00 (see global configuration registers, table 214, address 0x25).
363 8051 flash write timing t6 t1 t5 t3 t4 t2 t7 fa[17:8] data out fa[17:8] fa[7:0] fa[7:0] fale nfwr fad[7:0] fa[17:8] figure 73 - 8051 flash write timing table 249 - flash write timing parameters 8051 clock = 12 mhz parameter @12mhz min typ max units t1 address valid to fale low 38 42 ns t2 address hold following fale low 38 41 ns t3 fale low to nfwr low 110 124 140 ns t4 nfwr pulse width 300 332 ns t5 nfwr high to fale high 70 85 100 ns t6 data valid to nfwr falling edge 70 84 ns t7 data hold following nfwr 150 172 ns 8051 clock =24 mhz parameter @ 24 mhz min typ max units t1 address valid to fale low 14 20 ns t2 address hold following fale low 18 22 ns t3 fale low to nfwr low 48 62 76 ns t4 nfwr pulse width 130 162 ns t5 nfwr high to fale high 40 50 60 ns t6 data valid to nfwr falling edge 30 41 ns t7 data hold following nfwr 60 84 ns min and max delays shown for an 8051 clock of 12 mhz and 24 mhz as indicated. device mode register bits [1:0] = 00 (see global configuration registers, table 214, address 0x25).
364 ps/2 channel receive timing diagram t7 t2 t2 t3 t4 t3 t4 t7 t5 t10 t11 t1 t6 t8 t9 t12 b7 b0 b1 b2 b3 b4 b5 b6 p s wr_clk wr_data wr_clk wr_data note1 ps2_clk ps2_dat ps2_en ps2_t/r rdata_rdy read rx reg interrupt figure 74 - ps/2 channel receive timing diagram ps/2 channel reception parameters parameter min typ max units t1 the ps2 channel?s clk and data lines are floated following ps2_en=1 and ps2_t/r=0. 100 ns t2 period of clk 60 302 us t3 duration of clk high (active) 30 151 us t4 duration of clk low (inactive) 30 151 us t5 data setup time to falling edge of clk. FDC37N972 samples the data line on the falling clk edge. 1 us t6 data hold time from falling edge of clk. FDC37N972 samples the data line on the falling clk edge. 2 us t7 duration of data frame. falling edge of start bit clk (1st clk) to falling edge of parity bit clk (10th clk). 2.002 ms t8 falling edge of 11th clk to rdata_rdy asserted. 1.6 us
365 parameter min typ max units t9 trailing edge of the 8051?s rd signal of the receive register to rdata_rdy bit deasserted. 100 ns t10 trailing edge of the 8051?s rd signal of the receive register to the clk line released to high-z. 100 ns t11 the ps2 channel?s clk and data lines are driven to the values stored in the wr_clk and wr_data bits of the control register when ps2_en is written to 0. 100 ns t12 rdata_rdy asserted to interrupt generated. note1- interrupt is cleared by reading the 8051 int0 source register. 100 ns
366 ps/2 channel transmit timing diagram t6 t6 t10 t7 t7 t8 t8 t9 t9 t10 t2 t5 t1 t4 t11 t14 t16 t12 t3 t13 t15 p b0 b1 b2 b3 orion005 b4 b5 b6 b7 s 1 2 11 note1 10 ps2_clk ps2_dat ps2_en ps2_t/r xmit_idle rdata_rdy write tx reg interrupt figure 75 - ps/2 channel transmit timing diagram ps/2 channel transmission timing parameters parameter min typ max units t1 the ps2 channel?s clk and data lines are floated following ps2_en=1 and ps2_t/r=0. 100 ns t2 ps2_t/r bit set to clk driven low preparing the ps2 channel for data transmission. 100 ns t3 clk line floated to xmit_idle bit deasserted. 1.7 us t4 trailing edge of 8051 wr of transmit register to data line driven low. 45 90 ns t5 trailing edge of 8051 wr of transmit register to clk line floated. 90 130 ns
367 parameter min typ max units t6 initiation of start of transmit cycle by the ps2 channel controller to the auxilliary peripheral?s responding by latching the start bit and driving the clk line low. 0.002 25.003 ms t7 period of clk 60 302 us t8 duration of clk high (active) 30 151 us t9 duration of clk low (inactive) 30 151 us t10 duration of data frame. falling edge of start bit clk (1st clk) to falling edge of parity bit clk (10th clk). 2.002 ms t11 data output by FDC37N972 following the falling edge of clk. the auxilliary peripheral device samples data following the rising edge of clk. 3.5 7.1 us t12 rising edge following the 11th falling clock edge to ps_t/r bit driven low. 400 800 ns t13 trailing edge of ps_t/r to xmit_idle bit asserted. 100 ns t14 data released to high-z following the ps2_t/r bit going low. 100 ns t15 xmit_idle bit driven high to interrupt generated. note1- interrupt is cleared by reading the 8051 int0 source register. 100 ns t16 the ps2 channel?s clk and data lines are driven to the values stored in the wr_clk and wr_data bits of the control register when ps2_en is written to 0. 100 ns
368 ps/2 channel ?bit-bang? timing t1 t1 note1 note1 note2 note2 ps2_clk1 ps2_dat interrupt ps2_en figure 76 - ps/2 channel ?bit-bang? transmit timing diagram table 250 - ps/2 channel ?bit-bang? transmit timing parameters parameter min typ max units t1 falling edge of clk to interrupt generated. 1.1 us 8051 firmware responds to interrupt and drives data line before rising edge of ps2_clk line. 8051 firmware clears interrupt by reading the 8051 int0 source register. t1 t1 note1 note1 note2 note2 ps2_clk1 ps2_dat interrupt ps2_en figure 77 - ps/2 channel ?bit-bang? receive timing diagram table 251 - ps/2 channel ?bit-bang? receive timing parameters parameter min typ max units t1 falling edge of clk to interrupt generated. 100 ns 8051 firmware responds to interrupt and latches data line before rising edge of ps2_clk line. 8051 firmware clears interrupt by reading the 8051 int0 source register.
369 pwrgd vcc2 clocki 10 m s 3v min. figure 78 ? power-fail event parameter min typ max units valid clocki to pwrgd deasserted 10 s pwrgd vcc2 3v clocki 10 m s min. figure 79 - vcc2 power-up timing parameter min typ max units valid clocki to pwrgd asserted 10 s vcc1_pwrgd vcc1 3v 3v 1 m s min. 1 m s min. figure 80 - vcc1_pwrgd timing parameter min typ max units valid vcc1 to vcc1_pwrgd deasserted 1 s valid vcc1 to vcc1_pwrgd asserted 1 s
370 in circuit test (ict) the ict impedance measurement is installed in the production test program. it is run after opens/shorts (vcc still at 0v). the measurement forces 0.2v on all ict pins simultaneously and measures for less than 0.2ua. a failure at this time branches to a pin by pin test that forces 0.2v and measures 0.2ua on individual pins. any pin greater then 0.2ua is considered a failure. table 252 - ict pin map pin # pin name pin # pin name 2 nds1 / out5 57 sa3 3 nmtr1 / out6 59 sa5 9 ndir 61 sa7 14 nindex 63 sa9 15 ntrk0 76 nnows 16 nwprtprt 77 nior 17 nrdata 78 niow 18 ndskchg 81 sd1 19 fpd 84 sd3 20 irtx 86 sd5 24 kso11 88 sd7 25 kso10 90 ndack0 26 kso9 91 drq0 27 kso8 92 ndack1 28 kso7 93 drq1 30 kso6 96 nromcs 31 kso5 97 nmemrd 32 kso4 98 nmemwr 33 kso3 99 pci_clk 34 kso2 109 vcc1_pwrgd 35 kso1 110 npwr_led 36 kso0 141 rxd2 / gpio8 37 ks17 151 in3 38 ks16 154 in6 39 ks15 157 xosel 40 ks14 190 gpio6 41 ks13 193 nea 42 ks12 194 mode 43 ks11 195 ab_data 44 ks10 196 ab_clk 48 imdat 197 nbat_led 50 kclk 203 out7 51 kdat 204 gpio16 52 emclk 206 gpio17 53 emdat 207 gpio18 55 sa1 208 gpio19
371 board level connectivity test mode to allow the FDC37N972 to be tested efficiently at board level, a test mode is provided to allow board level connectivity testing to be carried out. the board level connectivity test mode (and tree mode) is defined below. the and tree test mode is enabled and latched by: iowb = iorb = memwrb = memrdb = 0 and pwrgd = 1 when activated, this test mode forces all output and bidirectional pins to function as inputs. all these input pins are now input to an and tree which is output on nreset_out. this will allow one single input pin, when switched, to toggle the nreset_out output, if all other input pins are high. this test mode is disabled/reset by a por.
372 figure 81 - 208 pin flex bga 15.0x15.0x1.10 (preliminary)
373 a a1 a2 d d1 e e1 h min 0.05 1.35 29.90 27.90 29.90 27.90 0.09 nom 30.00 28.00 30.00 28.00 max 1.6 0.15 1.45 30.10 28.10 30.10 28.10 0.230 nom 0.60 1.00 0.50bsc min 0.45 0 0.17 0.08 0.08 max 0.75 7 0.27 0.20 0.08 l l1 e 0 w r1 r2 ccc notes: 1) coplanarity is 0.080 mm or 3.2 mils maximum 2) tolerance on the position of the leads is 0.080 mm maximum 3) package body dimensions d1 and e1 do not include the mold protrusion. maximum mold protrusion is 0.25 mm 5) details of pin 1 identifier are optional but must be located within the zone indicated 6) controlling dimension: millimeter 4) dimensions for foot length l measured at the gauge plane 0.25 mm above the seating plane figure 82 - 208 pin tqfp package outline
374 appendix a high-performance 8051 cycle timing and instruction set the high-performance 8051 processor offers increased performance by executing instructions in a 4-clock cycle, as opposed to the standard 8051. the shortened bus timing improves the instruction execution rate for most instructions by a factor of three over the standard 8051 architectutres. some instructions require a different number of instruction cycles on the high-performance 8051than they do on the standard 8051. in the standard 8051, all instructions except for mul and div take one or two instruction cycles to complete. int the high-performance 8051 architecture, instructions can take between one and five instructions to complete. the average speed improvement for the entire instruction set is approximately 2.5x. legend for instruction set table symbol function a accumulator rn register r7-r0 direct internal register address @ri internal register pointed to by r0 or r1 (except movx) rel two?s complement offset byte bit direct bit address #data 8-bit constant #data 16 16-bit constant addr 16 16-bit destination address addr 11 11-bit destination address table 253 - 8051 instruction set instruction description byte count instruction cycles hex code arithmetic add a, rn add register to a 1 1 28-2f add a, direct add direct byte to a 2 2 25 add a, @ri add data memory to a 1 1 26-27 add a, #data add immediate to a 2 2 24 addc a, rn add register to a with carry 1 1 38-3f addc a, direct add direct byte to a with carry 2 2 35 addc a, @ri add data memory to a with carry 1 1 36-37 addc a, #data add immediate to a with carry 2 2 34
375 instruction description byte count instruction cycles hex code subb a, rn subtract register from a with borrow 1 1 98-9f subb a, direct subtract direct byte from a with borrow 2 2 95 subb a, @ri subtract data memory from a with borrow 1 1 96-97 subb a, #data subtract immediate from a with borrow 2 2 94 inc a increment a 1 1 04 inc rn increment register 1 1 08-0f inc direct increment direct byte 2 2 05 inc @ri increment data memory 1 1 06-07 dec a decrement a 1 1 14 dec rn decrement register 1 1 18-1f dec direct decrement direct byte 2 2 15 dec @ri decrement data memory 1 1 16-17 inc dptr increment data pointer 1 3 a3 mul ab multiply a by b 1 5 a4 div ab divide a by b 1 5 84 da a decimal adjust a 1 1 d4 logical anl a, rn and register to a 1 1 58-5f anl a, direct and direct byte to a 2 2 55 anl a, @ri and data memory to a 1 1 56-57 anl a, #data and immediate to a 2 2 54 anl direct, a and a to direct byte 2 2 52 anl direct, #data and immediate data to direct byte 3 3 53 orl a, rn or register to a 1 1 48-4f orl a, direct or direct byte to a 2 2 45 orl a, @ri or data memory to a 1 1 46-47 orl a, #data or immediate to a 2 2 44 orl direct, a or a to direct byte 2 2 42 orl direct, #data or immediate data to direct byte 3 3 43 xorl a, rn exclusive-or register to a 1 1 68-6f xorl a, direct exclusive-or direct byte to a 2 2 65 xorl a, @ri exclusive-or data memory to a 1 1 66-67
376 instruction description byte count instruction cycles hex code xorl a, #data exclusive-or immediate to a 2 2 64 xorl direct, a exclusive-or a to direct byte 3 3 63 xorl direct, #data exclusive-or immediate to direct byte 3 3 63 clr a clear a 1 1 e4 cpl a complement a 1 1 f4 rl a rotate a left 1 1 23 rlc a rotate a left through carry 1 1 33 rr a rotate a right 1 1 03 rrc a rotate a right through carry 1 1 13 data transfer mov a, rn move register to a 1 1 e8-ef mov a, direct move direct byte to a 2 2 e5 mov a, @ri move data memory to a 1 1 e6-e7 mov a, #data move immediate to a 2 2 74 mov rn, a move a to reigster 1 1 f8-ff mov rn, direct move direct byte to register 2 2 a8-af mov rn, #data move immediate to register 2 2 78-7f mov direct, a move a to direct byte 2 2 f5 mov direct, rn move register to direct byte 2 2 88-8f mov direct, direct move direct byte to direct byte 3 3 85 mov direct, @ri move data memory to direct byte 2 2 86-87 mov direct, #data move immediate to direct byte 3 3 75 mov @ri, a move a to data memory 1 1 f6-f7 mov @ri, direct move direct byte to data memory 2 2 a6-a7 mov @ri, #data move immediate to data memory 2 2 76-77 mov dptr, #data move immediate to data pointer 3 3 90 movc a, @a+dptr move code byte relative dptr to a 1 3 93
377 instruction description byte count instruction cycles hex code movc a, @a+pc move code byte relative pc to a 1 3 83 movx a, @ri move external data (a8) to a 1 2-9 e2-e3 movx a, @dptr move external data (a16) to a 1 2-9 e0 movx @ri, a move a to external data (a8) 1 2-9 f2-f3 movx @dptr, a move a to external data (a16) 1 2-9 f0 push direct push direct byte onto stack 2 2 c0 pop direct pop direct byte from stack 2 2 d0 xch a, rn exchange a and register 1 1 c8-cf xch a, direct exchange a and direct byte 2 2 c5 xch a, @ri exchange a and data memory 1 1 c6-c7 xchd a, @ri exchange a and data memory nibble 1 1 d6-d7 boolean clr c clear carry 1 1 c3 clr bit clear direct bit 2 2 c2 setb c set carry 1 1 d3 setb bit set direct bit 2 2 d2 cpl c complement carry 1 1 b3 cpl bit complement direct bit 2 2 b2 anl c, bit and direct bit to carry 2 2 82 anl c, /bit and direct bit inverse to carry 2 2 b0 orl c, bit or direct bit to carry 2 2 72 orl c, /bit or direct bit inverse to carry 2 2 a0 mov c, bit move direct bit to carry 2 2 a2 mov bit, c move carry to direct bit 2 2 92 branching acall addr 11 absolute call to subroutine 2 3 11-f1 lcall addr 16 long call to subroutine 3 4 12 ret return from subroutine 1 4 22 reti return from interrupt 1 4 32
378 instruction description byte count instruction cycles hex code ajmp addr 11 absolute jump unconditional 2 3 01-e1 ljmp addr 16 long jump unconditional 3 4 02 sjmp rel short jump (relative address) 2 3 80 jc rel jump on carry = 1 2 3 40 jnc rel jump on carry = 0 2 3 50 jb bit, rel jump on direct bit = 1 3 4 20 jnb bit, rel jump on direct bit = 0 3 4 30 jmp @a+dptr jump indirect relative dptr 1 3 73 jz rel jump on accumulator = 0 2 3 60 jnz rel jump on accumulator /= 0 2 3 70 cjne a, direct, rel compare a, direct jne relative 3 4 b5 cjne a, #d, rel compare a, immediate jne relative 3 4 b4 cjne rn, #d, rel compare reg, immediate jne relative 3 4 b8-bf cjne @ri, #d, rel compare ind, immediate jne relative 3 4 b6-b7 djnz rn, rel decrement register, jnz relative 2 3 d8-df djnz direct, rel decrement direct byte, jnz relative 3 4 d5 miscellaneous nop no operation 1 1 00
379 appendix b high performance 8051 extended interrupt unit interrupts the exif, eicon, eie, and eip registers provide flags, enable control, and priority control for the extended interrupt unit in the FDC37N972 high-performance 8051. interrupt processing when an enabled interrupt occurs, the cpu vectors to the address of the interrupt service routine (isr) associated with that interrupt (see table 92 - 8051 interrupts on page 169 ). the cpu executes the isr to completion unless another interrupt of higher priority occurs. each isr ends with a reti (return from interrupt) instruction. after executing the reti, the cpu returns to the next instruction that would have been executed if the interrupt had not occurred. an isr can only be interrupted by a higher priority interrupt. that is, an isr for a low-level interrupt can only be interrupted by high-level interrupt. an isr for a high-level interrupt can only be interrupted by the power-fail interrupt (extended interrupt unit only). the 8051 always completes the instruction in progress before servicing an interrupt. if the instruction in progress is reti, or a write access to any of the ip, ie, eip, or eie sfrs, the 8051 completes one additional instruction before servicing the interrupt. interrupt masking the ea bit in the ie sfr (ie.7) is a global enable for all interrupts except the power-fail interrupt. when ea = 1, each interrupt is enabled/masked by its individual enable bit. when ea = 0, all interrupts are masked. the only exception is the power-fail interrupt, which is not affected by the ea bit. when epfi = 1, the power-fail interrupt is enabled, regardless of the state of the ea bit. table 92 on page 169 provides a summary of interrupt sources, flags, enables, and priorities. interrupt priorities there are two stages of interrupt priority assignment, interrupt level and natural priority. the interrupt level (highest, high, or low) takes precedence over natural priority. the power-fail interrupt, if enabled, always has highest priority and is the only interrupt that can have highest priority. all other interrupts can be assigned either high or low priority. in addition to an assigned priority level (high or low), each interrupt also has a natural priority, as listed in table 92 - on page 169 . simultaneous interrupts with the same priority level (for example, both high) are resolved according to their natural priority. for example, if int0_n and int2 are both programmed as high priority, int0_n takes precedence. once an interrupt is being serviced, only an interrupt of higher priority level can interrupt the service routine of the interrupt currently being serviced. interrupt sampling the internal timers and serial ports generate interrupts by setting their respective sfr interrupt flag bits. external interrupts are sampled once per instruction cycle.
380 int0_n and int1_n are both active low and can be programmed to be either edge-sensitive or level-sensitive, through the it0 and it1 bits in the tcon sfr. for example, when it0 = 0, int0_n is level-sensitive and the 8051 sets the ie0 flag when the int0_n pin is sampled low. when it0 = 1, int0_n is edge-sensitive and 8051 sets the ie0 flag when the int0_n pin is sampled high then low on consecutive samples. the remaining four external interrupts are edge- sensitive only. int2 and int4 are active high, int3_n and int5_n are active low. the power-fail (pfi) interrupt is edge-sensitive, active high, and sampled once per instruction cycle. to ensure that edge-sensitive interrupts are detected, the corresponding ports should be held high for 4 clk cycles and then low for 4 clk cycles. level- sensitive interrupts are not latched and must remain active until serviced. interrupt latency interrupt response time depends on the current state of the 8051. the fastest response time is 5 instruction cycles: 1 to detect the interrupt, and 4 to perform the lcall to the isr. the maximum latency (13 instruction cycles) occurs when the 8051 is currently executing a reti instruction followed by a mul or div instruction. the 13 instruction cycles in this case are: 1 to detect the interrupt, 3 to complete the reti, 5 to execute the div or mul, and 4 to execute the lcall to the isr. for the maximum latency case, the response time is 13 x 4 = 52 clk cycles. dual data pointers the high-performance 8051 in the FDC37N972 employs dual data pointers to accelerate data memory block moves. the standard 8051 data pointer (dptr) is a 16-bit value used to address external ram or peripherals. the FDC37N972 maintains the standard data pointer as dptr0 at sfr locations 82h and 83h. it is not necessary to modify code to use dptr0. the FDC37N972 adds a second data pointer (dptr1) at sfr locations 84h and 85h. the sel bit in the dptr select register, dps (sfr 86h), selects the active pointer (see sections dpl1 , dph1 and dps below). all dptr-related instructions use the currently selected data pointer. to switch the active pointer, toggle the sel bit. the fastest way to do so is to use the increment instruction (inc dps). this requires only one instruction to switch from a source address to a destination address, saving application code from having to save source and destination addresses when doing a block move. timer 2 overview the high-performance 8051 in the FDC37N972 includes a third timer/counter (timer 2). timer 2 runs only in 16-bit mode and offers several capabilities not available with timers 0 and 1. the modes available with timer 2 are 16-bit auto-reload timer/counter and baud rate generator. the sfrs associated with timer 2 are: t2con (sfr c8h) rcap2l (sfr cah) ? used as the 16-bit lsb reload value when timer 2 is configured for auto- reload mode. rcap2h (sfr cbh) ? used as the 16-bit msb reload value when timer 2 is configured for auto- reload mode. tl2 (sfr cch) ? lower 8 bits of 16-bit count. th2 (sfr cdh) ? upper 8 bits of 16-bit count.
381 table 254 summarizes how the t2con sfr bits ( table 259 ) determine the timer 2 operating mode. table 254 - timer 2 mode control summary rclk tclk tr2 mode 0 0 1 16-bit timer/counter w/auto-reload 1 x 1 baud rate generator x 1 1 baud rate generator x x 0 off 16-bit timer/counter mode with auto-reload figure 83 illustrates how timer 2 operates in timer/counter mode with auto-reload. the 16-bit timer counts clk cycles (divided by 4 or 12). the tr2 bit enables the counter. when the count increments from ffffh, the overflow occurs. the overflow causes the tf2 flag is set, and t2_out goes high for one clk cycle. the overflow also causes the preloaded start value in the rcap2l and rcap2h registers to be reloaded into the tl2 and th2 registers. figure 83 - timer 2 timer/counter with auto-reload baud rate generator mode setting either rclk or tclk to 1 configures timer 2 to generate baud rates for serial port 0 in serial mode 1 or 3. in baud rate generator mode, timer 2 functions in auto-reload mode. however, instead of setting the tf2 flag, the counter overflow is used to generate a shift clock for the serial port function. as in normal auto-reload mode, the overflow also causes the preloaded start value in the rcap2l and rcap2h registers to be reloaded into the tl2 and th2 registers. when either tclk = 1 or rclk = 1, timer 2 is forced into auto-reload operation. the counter time base in baud rate generator mode is clk/2. divide by 12 divide by 4 clk tr2 t2m tl2 th2 rcap2l rcap2h clk tf2 int 0 1
382 special function registers the following sfrs are not part of the sandard 8051 architecture. dpl1 the dpl1 register ( table 255 ) is the lsb of dptr1 (see the section interrupts above). table 255 - dpl1 register - sfr 84h sfr address 84h power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 type r/w r/w r/w r/w r/w r/w r/w r/w bit name a7 a6 a5 a4 a3 a2 a1 a0 dph1 the dph1 register ( table 256 ) is the msb of dptr1 (see the section interrupts above). table 256 - dph1 register - sfr 85h sfr address 85h power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 type r/w r/w r/w r/w r/w r/w r/w r/w bit name a15 a14 a13 a12 a11 a10 a9 a8 dps the dps register ( table 257 ) is used to select the active dptr (see the section interrupts above). table 257 - dps register - sfr 86h sfr address 86h power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 type r r r r r r r r/w bit name reserved sel 1 note 1 when sel = ?0?, instructions that use the dptr will use dpl0 and dph0. when sel = ?1?, instructions that use the dptr will use dpl1 and dph1.
383 ckcon the default timer clock scheme for the dw8051 timers is 12 clk cycles per increment, the same as in the standard 8051. however, in the dw8051, the instruction cycle is 4 clk cycles. using the default rate (12 clocks per timer increment) allows existing application code with real-time dependencies, such as baud rate, to operate properly. however, applications that require fast timing can set the timers to increment every 4 clk cycles by setting bits in the clock control register (ckcon) at sfr location 8eh ( table 258 and table 259 ). the ckcon bits that control the timer clock rates are: ckcon bit counter/timer 5 timer 2 4 timer 1 3 timer 0 when a ckcon register bit is set to 1, the associated counter increments at 4-clk intervals. when a ckcon bit is cleared, the associated counter increments at 12-clk intervals. the timer controls are independent of each other. the default setting for all three timers is 0 (12-clk intervals). these bits have no effect in counter mode. table 258 - ckcon register - sfr 8eh sfr address 8eh power vcc1 default 0x01 d7 d6 d5 d4 d3 d2 d1 d0 type r r r/w r/w r/w r/w r/w r/w bit name reserved t2m t1m t0m md2 md1 md0 table 259 - ckcon register bit descriptions bit function ckcon.7-6 reserved ckcon.5 t2m. timer 2 clock select. when t2m = 0, timer 2 uses clk/12 (for compatibility with 80c32); when t2m = 1, timer 2 uses clk/4. this bit has no effect when timer 2 is configured for baud rate generation. ckcon.4 t1m. timer 1 clock select. when t1m = 0, timer 1 uses clk/12 (for compatibility with 80c32); when t1m = 1, timer 1 uses clk/4. ckcon.3 t0m. timer 0 clock select. when t0m = 0, timer 0 uses clk/12 (for compatibility with 80c32); when t0m = 1, timer 0 uses clk/4. ckcon.2-0 md2, md1, md0 -- control the number of cycles to be used for external movx instructions.
384 mpage the mpage special function register ( table 260 ) replaces the function of the port 2 latch in the FDC37N972. during movx a, @ri and movx @ri, a instructions, the 8051 places the contents of the mpage register on the upper eight address bits. this provides the paging function that is normally provided by the port 2 latch. table 260 - mpage register ? sfr 92h sfr address 92h power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 type r/w r/w r/w r/w r/w r/w r/w r/w bit name a15 a14 a13 a12 a11 a10 a9 a8 t2con the t2con register ( table 261 and table 263 ) is used to configure timer 2 (see the section interrupts above). table 261 ? t2con register - sfr c8h sfr address c8h power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 type r/w r/w r/w r/w r/w r/w r/w r/w bit name tf2 reserv ed rclk tclk reserv ed tr2 reserved table 263 ? t2con register bit descriptions bit function t2con.7 tf2 timer 2 overflow flag. hardware will set tf2 when the timer 2 overflows from ffffh. tf2 must be cleared to 0 by the software. tf2 will only be set to a 1 if rclk and tclk are both cleared to 0. writing a 1 to tf2 forces a timer 2 interrupt if enabled. t2con.6 reserved. this bit should be written as ?0?. t2con.5 rclk receive clock flag. determines whether timer 1 or timer 2 is used for serial port 0 timing of received data in serial mode 1 or 3. rclk =1 selects timer 2 overflow as the receive clock. rclk =0 selects timer 1 overflow as the receive clock. t2con.4 tclk transmit clock flag. determines whether timer 1 or timer 2 is used for serial port 0 timing of transmit data in
385 bit function serial mode 1 or 3. rclk =1 selects timer 2 overflow as the transmit clock. rclk =0 selects timer 1 overflow as the transmit clock. t2con.3 reserved. this bit should be written as ?0?. t2con.2 tr2. timer 2 run control flag. tr2 = 1 starts timer 2. tr2 = 0 stops timer 2. t2con.1-0 reserved. this bit should be written as ?0?. rcap2l the rcap2l register ( table 263 ) is the 16-bit lsb reload value (rv[7:0]) when timer 2 is configured for auto-reload mode (see the section interrupts above). table 263 - rcap2l register ? sfr cah sfr address cah power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 type r/w r/w r/w r/w r/w r/w r/w r/w bit name rv7 rv6 rv5 rv4 rv3 rv2 rv1 rv0 rcap2h the rcap2h register ( table 264 ) is the 16-bit msb reload value (rv[15:8]) when timer 2 is configured for auto-reload mode (see the section interrupts above). table 264 - rcap2h register - sfr cbh sfr address cbh power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 type r/w r/w r/w r/w r/w r/w r/w r/w bit name rv15 rv14 rv13 rv12 rv11 rv10 rv9 rv8
386 tl2 the tl2 register ( table 265 ) is the 16-bit lsb timer 2 count value (cv[7:0]) (see the section interrupts above). table 265 - tl2 register - sfr cch sfr address cch power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 type r/w r/w r/w r/w r/w r/w r/w r/w bit name cv7 cv6 cv5 cv4 cv3 cv2 cv1 cv0 th2 the th2 register (table 266 table 266 ) is the 16-bit msb timer 2 count value (cv[15:8]) (see the section interrupts above). table 266 - th2 register - sfr cdh sfr address cdh power vcc1 default 0x00 d7 d6 d5 d4 d3 d2 d1 d0 type r/w r/w r/w r/w r/w r/w r/w r/w bit name cv15 cv14 cv13 cv12 cv11 cv10 cv9 cv8 exif the exif register (table 268 and table 269) contains the external interrupt flags for the extended interrupt unit (see the section interrupts above). table 267 - exif register - sfr 91h sfr address 91h power vcc1 default 0x08 d7 d6 d5 d4 d3 d2 d1 d0 type r/w r/w r/w r/w r r r r bit name ie5 ie4 ie3 ie2 reserved
387 table 268 - exif register bit description s bit function exif.7 ie5 external interrupt 5 flag. ie5 = 1 indicates a falling edge was detected at the int5_n pin. ie5 must be cleared by software. setting ie5 in software generates an interrupt, if enabled. exif.6 ie4 external interrupt 4 flag. ie4 = 1 indicates a rising edge was detected at the int4 pin. ie4 must be cleared by software. setting ie4 in software generates an interrupt, if enabled. exif.5 ie3 external interrupt 3 flag. ie3 = 1 indicates a falling edge was detected at the int3_n pin. ie3 must be cleared by software. setting ie3 in software generates an interrupt, if enabled. exif.4 ie2 external interrupt 2 flag. ie2 = 1 indicates a rising edge was detected at the int2 pin. ie2 must be cleared by software. setting ie2 in software generates an interrupt, if enabled. exif.3 reserved. read as ?1?. exif.2-0 reserved. read as ?0?. eicon the eicon register ( table 269 and table 270 ) contains pfi and serial port 1 controls for the extended interrupt unit (see the section interrupts above). table 269 - eicon register - sfr d8h sfr address d8h power vcc1 default 0x40 d7 d6 d5 d4 d3 d2 d1 d0 type r/w r/w r/w r/w r r r r bit name smod1 reserv ed epfi pfi reserved table 270 - eicon register bit descriptions bit function eicon.7 smod1 serial port 1 baud rate doubler enable. when smod1 = 1, the baud rate for serial port 1 is doubled. eicon.6 reserved. read as ?1?. eicon.5 epfi enable power-fail interrupt. epfi = 0 disables power- fail interrupt (pfi). epfi = 1 enables interrupts generated by the pfi pin. eicon.4 pfi power-fail interrupt flag. pfi = 1 indicates a power-fail
388 bit function interrupt was detected at the pfi pin. pfi must be cleared by software before exiting the interrupt service routine. otherwise, the interrupt occurs again. setting pfi in software generates a power-fail interrupt, if enabled. eicon.3-0 reserved. read as ?0?. eie the eie register (table 273 and table 275) contains the external interrupt enables for the extended interrupt unit (see the section interrupts above). table 271 - eie register - sfr e8h sfr address e8h power vcc1 default 0xe0 d7 d6 d5 d4 d3 d2 d1 d0 type r r r r r/w r/w r/w r/w bit name reserved ex5 ex4 ex3 ex2 table 272 - eie register bit descriptions bit function eie.7-5 reserved. read as ?1?. eie.4 reserved. read and write as ?0?. eie.3 ex5 enable external interrupt 5. ex5 = 0 disables external interrupt 5 (int5_n). ex5 = 1 enables interrupts generated by the int5_n pin. eie.2 ex4 enable external interrupt 4. ex4 = 0 disables external interrupt 4 (int4). ex4 = 1 enables interrupts generated by the int4 pin. eie.1 ex3 enable external interrupt 3. ex3 = 0 disables external interrupt 3 (int3_n). ex3 = 1 enables interrupts generated by the int3_n pin. eie.0 ex2 enable external interrupt 2. ex2 = 0 disables external interrupt 2 (int2). ex2 = 1 enables interrupts generated by the int2 pin.
389 eip the eip register (table 273 and table 274) contains the external interrupt priority controls for the extended interrupt unit (see the section interrupts above). table 273 - eip register - sfr f8h sfr address f8h power vcc1 default 0xe0 d7 d6 d5 d4 d3 d2 d1 d0 type r r r r r/w r/w r/w r/w bit name reserved px5 px4 px3 px2 table 274 - eip regsiter bit descriptions bit function eip.7-5 reserved. read as ?1?. eip.4 reserved. read and write as ?0?. eip.3 px5 external interrupt 5 priority control. px5 = 0 sets external interrupt 5 (int5_n) to low priority. px5 = 1 sets external interrupt 5 to high priority. eip.2 px4 external interrupt 4 priority control. px4 = 0 sets external interrupt 4 (int4) to low priority. px2 = 1 sets external interrupt 4 to high priority. eip.1 px3 external interrupt 3 priority control. px3 = 0 sets external interrupt 3 (int3_n) to low priority. px3 = 1 sets external interrupt 3 to high priority. eip.0 px2 external interrupt 2 priority control. px2 = 0 sets external interrupt 2 (int2) to low priority. px2 = 1 sets external interrupt 2 to high priority.
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